公开(公告)号：US10509727B1

公开(公告)日：2019-12-17

申请号：US16125780

申请日：2018-09-10

Applicant: MEDIATEK INC.

Inventor： Sheng-Ju Wei ,  Jia-Ming Chen ,  I-Cheng Cheng ,  Shun-Chieh Chang

IPC: G06F12/00 ,  G06F12/0888 ,  G06F12/0875

Abstract: A method and an apparatus for performing task-level cache management in an electronic device are provided. The method may be applied to a processing circuit of the electronic device, and may include: before a task of a plurality of tasks runs on a processor core, performing at least one checking operation on the task to generate at least one checking result, wherein the at least one checking result indicates whether the task is a risky task with risk of evicting cached data of an urgent task from a cache, and the cache is dedicated to a set of processor cores including the processor core; and according to the at least one checking result, determining whether to temporarily limit cache access permission of the processor core during a time period in which the task runs on the processor core, for preventing cache eviction of the cache due to the task.

公开(公告)号：US20170300427A1

公开(公告)日：2017-10-19

申请号：US15487402

申请日：2017-04-13

Applicant: MEDIATEK INC.

Inventor： Chien-Hung Lin ,  Ming-Ju Wu ,  Wei-Hao Chiao ,  Kun-Geng Lee ,  Shun-Chieh Chang ,  Ming-Ku Chang ,  Chia-Hao Hsu ,  Pi-Cheng Hsiao

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/602 ,  G06F2212/621

Abstract: A multi-processor system with cache sharing has a plurality of processor sub-systems and a cache coherence interconnect circuit. The processor sub-systems have a first processor sub-system and a second processor sub-system. The first processor sub-system includes at least one first processor and a first cache coupled to the at least one first processor. The second processor sub-system includes at least one second processor and a second cache coupled to the at least one second processor. The cache coherence interconnect circuit is coupled to the processor sub-systems, and used to obtain a cache line data from an evicted cache line in the first cache, and transfer the obtained cache line data to the second cache for storage.