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    Timing Error Detector with Diversity Loop Detector Decision Feedback
    11.
    发明申请
    Timing Error Detector with Diversity Loop Detector Decision Feedback 有权
    具有分集环路检测器判定反馈的定时误差检测器

    公开(公告)号：US20140362463A1

    公开(公告)日：2014-12-11

    申请号：US13941464

    申请日：2013-07-13

    Applicant: LSI Corporation

    Inventor： Bruce Wilson ,  Yang Han ,  Yu Kou ,  Rui Cao

    IPC: G11B20/14 ,  G11B5/09

    CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2220/2516

    Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

    Abstract translation: 本公开的方面涉及用于检测定时误差的装置，包括模数转换器电路，分集环路检测器和定时误差计算电路。 模数转换器电路可操作以将输入信号转换为一系列数字采样。 分集环路检测器可操作以将数据检测算法应用于在不同相位偏移处从一系列数字样本导出的多个信号，以选择相位偏移中的一个，并产生具有所选相位偏移的检测输出。 定时误差计算电路可用于至少部分地基于所选择的相位偏移来计算模数转换器电路的定时误差。

    Timing error detector with diversity loop detector decision feedback
    14.
    发明授权
    Timing error detector with diversity loop detector decision feedback 有权
    具有分集环路检测器判定反馈的定时误差检测器

    公开(公告)号：US09275655B2

    公开(公告)日：2016-03-01

    申请号：US13941464

    申请日：2013-07-13

    Applicant: LSI Corporation

    Inventor： Bruce Wilson ,  Yang Han ,  Yu Kou ,  Rui Cao

    IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10

    CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2220/2516

    Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

    Abstract translation: 本公开的方面涉及用于检测定时误差的装置，包括模数转换器电路，分集环路检测器和定时误差计算电路。 模数转换器电路可操作以将输入信号转换为一系列数字采样。 分集环路检测器可操作以将数据检测算法应用于在不同相位偏移处从一系列数字样本导出的多个信号，以选择相位偏移中的一个，并产生具有所选相位偏移的检测输出。 定时误差计算电路可用于至少部分地基于所选择的相位偏移来计算模数转换器电路的定时误差。

    System and method to interleave memory
    15.
    发明授权
    System and method to interleave memory 有权
    用于交错内存的系统和方法

    公开(公告)号：US09208083B2

    公开(公告)日：2015-12-08

    申请号：US14169424

    申请日：2014-01-31

    Applicant: LSI Corporation

    Inventor： Yang Han ,  Zongwang Li ,  Shaohua Yang ,  Kaichi Zhang

    IPC: G06F12/00 ,  G06F12/06

    CPC classification number: G06F12/0607 ,  G11C7/1012 ,  G11C7/1042

    Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

    Abstract translation: 存储器交错装置包括第一和第二交织器。 第一交织器响应于扇区选择信号选择性地交织存储在第一存储器中的信息。 第二交织器响应于扇区选择信号选择性地交织存储在第二存储器中的信息。 第一交织器与第二交织器耦合。 存储器交错系统包括交织器和存储装置。 交织器与第一扇区尺寸和第二扇区尺寸相关联。 交织器响应于扇区选择信号选择性地交织存储在第一存储器和/或第二存储器中的信息。 存储装置响应于扇区选择信号选择性地向交织器提供第一掩蔽种子和/或第二掩蔽种子。 还公开了相应的方法。

    Systems and methods for loop pulse estimation
    17.
    发明授权
    Systems and methods for loop pulse estimation 有权
    环路脉冲估计的系统和方法

    公开(公告)号：US08929010B1

    公开(公告)日：2015-01-06

    申请号：US14029559

    申请日：2013-09-17

    Applicant: LSI Corporation

    Inventor： Rui Cao ,  Yu Kou ,  Xuebin Wu ,  Yang Han

    IPC: G11B20/10 ,  G11B5/035 ,  H04L25/03

    CPC classification number: H04L25/03885 ,  G11B5/09 ,  G11B20/10027 ,  H04L25/0212 ,  H04L25/0238 ,  H04L25/025

    Abstract: A data processing system includes a digital data input operable to receive digital data, a digital data values input operable to receive values of the digital data, a loop pulse response estimation circuit operable to calculate a loop pulse response based on the digital data and the values of the digital data and based at least in part on past values of the loop pulse response, and a scaling circuit operable to scale the loop pulse response based at least in part on an absolute sum of the loop pulse response to yield a scaled loop pulse response.

    Abstract translation: 数据处理系统包括可操作以接收数字数据的数字数据输入，可操作以接收数字数据值的数字数据值输入;循环脉冲响应估计电路，其可操作以基于数字数据和值计算环路脉冲响应 至少部分地基于环路脉冲响应的过去值，以及缩放电路，其可操作以至少部分地基于环路脉冲响应的绝对和来缩放环路脉冲响应，以产生缩放的环路脉冲 响应。

    Read Channel Sampling Utilizing Two Quantization Modules for Increased Sample Bit Width
    19.
    发明申请
    Read Channel Sampling Utilizing Two Quantization Modules for Increased Sample Bit Width 有权
    读取通道采样利用两个量化模块增加采样位宽度

    公开(公告)号：US20150228303A1

    公开(公告)日：2015-08-13

    申请号：US14198008

    申请日：2014-03-05

    Applicant: LSI Corporation

    Inventor： Xuebin Wu ,  Yang Han ,  Weijun Tan ,  Shaohua Yang

    IPC: G11B20/10

    CPC classification number: G11B20/10046 ,  G10L19/0208 ,  G11B5/012 ,  G11B5/5526 ,  G11B5/553 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/1403

    Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

    Abstract translation: 公开了一种由这种通信信道结构支持的通信信道结构和解码方法。 这样的通信信道包括被配置为对输入信号进行滤波的数字滤波器和被配置为量化滤波信号的两个量化器。 利用第一量化器来量化滤波后的信号以产生具有第一精度的第一量化样本，并且使用第二量化器量化滤波信号以产生具有第二精度的第二量化样本，其中第二精度不同于 第一精度。 通信信道还包括迭代解码器，其被配置为利用第一量化样本进行解码过程的第一全局迭代，并且利用第二量化样本进行解码过程的至少一个后续全局迭代。

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