知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.016 seconds)

    Technology for high performance buried contact and tungsten polycide gate integration
    11.
    发明授权
    Technology for high performance buried contact and tungsten polycide gate integration 失效
    技术用于高性能埋地接触和钨硅化合物门集成

    公开(公告)号：US5998269A

    公开(公告)日：1999-12-07

    申请号：US35139

    申请日：1998-03-05

    Applicant: Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

    Inventor： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

    IPC: H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/3215 ,  H01L21/335 ,  H01L21/74

    CPC classification number: H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

    Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

    Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

    Method of forming an embedded memory device
    13.
    发明授权
    Method of forming an embedded memory device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US09082705B2

    公开(公告)日：2015-07-14

    申请号：US13566710

    申请日：2012-08-03

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Semiconductor devices and methods for fabricating the same
    15.
    发明授权
    Semiconductor devices and methods for fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08012836B2

    公开(公告)日：2011-09-06

    申请号：US11528405

    申请日：2006-09-28

    Applicant: Kuo-Chyuan Tzeng ,  Jian-Yu Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chin-Yang Chang

    Inventor： Kuo-Chyuan Tzeng ,  Jian-Yu Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chin-Yang Chang

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10894

    Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件的示例性实施例包括在其中形成有多个隔离结构的衬底，其在衬底上限定第一和第二区域。 晶体管分别形成在第一和第二区域中的衬底的一部分上，其中第二区域中的晶体管仅在与衬底的漏极区相邻的衬底中仅形成一个凹坑掺杂区域。 第一电介质层形成在衬底上，覆盖形成在第一和第二区域中的晶体管。 通过第一介电层形成多个第一接触插塞，分别在第二区域中电连接晶体管的源极区域和漏极区域。 在第一电介质层上形成第二电介质层，其中形成有电容器，其中电容器电连接第一接触插塞之一。

    Securing device
    18.
    发明授权
    Securing device 失效
    固定装置

    公开(公告)号：US06909085B2

    公开(公告)日：2005-06-21

    申请号：US10456885

    申请日：2003-06-06

    Applicant: Kuo-Ching Huang

    Inventor： Kuo-Ching Huang

    IPC: H04N1/028 ,  H04N1/03 ,  H04N1/19 ,  H01J40/14 ,  H01J5/02

    CPC classification number: H04N1/03 ,  H04N2201/02456 ,  H04N2201/02474 ,  H04N2201/02485

    Abstract: A securing device includes a sustaining member, a plurality of threaded holes, and a plurality of screws. The sustaining member includes a clamped portion and a securing portion extending from the clamped portion. The clamped portion is interfaced between the photoelectric conversion device and the carriage module housing. The thickness of the clamped portion is even enough to keep the distance between the photoelectric conversion device and the carriage module housing constant, thereby assuring that the photoelectric conversion device is orthogonal to the central line of a lens in the carriage module housing. The securing portion is flexible so as to facilitate the assembling operation of the circuit board, the photoelectric conversion device and the carriage module housing by way of the threaded holes and screws.

    Abstract translation: 固定装置包括支撑构件，多个螺纹孔和多个螺钉。 保持构件包括夹紧部分和从夹紧部分延伸的固定部分。 夹持部分接合在光电转换装置和支架模块壳体之间。 夹持部分的厚度足以使光电转换装置和滑架模块壳体之间的距离恒定，从而确保光电转换装置与托架模块壳体中的透镜的中心线正交。 固定部分是柔性的，以便于通过螺纹孔和螺钉使电路板，光电转换装置和滑架模块壳体的组装操作。

    Integrated high performance MOS tunneling LED in ULSI technology
    19.
    发明授权
    Integrated high performance MOS tunneling LED in ULSI technology 失效
    集成高性能MOS隧道LED在ULSI技术

    公开(公告)号：US06806521B2

    公开(公告)日：2004-10-19

    申请号：US10338138

    申请日：2003-01-08

    Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang

    Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang

    IPC: H01L31062

    CPC classification number: H01L27/15 ,  H01L33/0004

    Abstract: A new method and structure for the combined creation of CMOS devices and LED devices. The process starts with a substrate over the surface of which are designated a first surface region for the creation of CMOS devices there-over and a second surface region for the creation of LED devices there-over. A relatively thick layer of gate oxide is created over the surface of the substrate. The first surface region is blocked by a mask of photoresist after which the second surface region is exposed to a plasma etch, thereby providing roughness to the surface of the relatively thick layer of gate oxide and reducing the thickness thereof. The blocking mask is removed, additional oxidation of the exposed surface creates a relatively thick layer of gate oxide over the first surface area and a relatively thin layer of gate oxide over the second surface area.

    Abstract translation: 一种用于组合创建CMOS器件和LED器件的新方法和结构。 该过程从其表面上的衬底指定为用于在其上形成CMOS器件的第一表面区域和用于在其上形成LED器件的第二表面区域开始。 在衬底的表面上形成较厚的栅极氧化层。 第一表面区域被光致抗蚀剂掩模阻挡，之后第二表面区域暴露于等离子体蚀刻，从而为栅极氧化物的较厚层的表面提供粗糙度并减小其厚度。 去除阻挡掩模，暴露表面的额外氧化在第一表面区域上形成相对厚的栅极氧化物层，并在第二表面区域上形成相当薄的栅极氧化物层。

    Method to evaluate hemisperical grain (HSG) polysilicon surface
    20.
    发明授权
    Method to evaluate hemisperical grain (HSG) polysilicon surface 有权
    评估半晶粒（HSG）多晶硅表面的方法

    公开(公告)号：US06194234B1

    公开(公告)日：2001-02-27

    申请号：US09324925

    申请日：1999-06-04

    Applicant: Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

    Inventor： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

    IPC: G01R3126

    CPC classification number: H01L22/12

    Abstract: A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2−W1 provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG. This new method can also be based on measuring the weight W of rejected or dropped PR or SOG after the surface of the HSG layer has been coated with a layer of either photoresist or SOG. The weight of the rejected or dropped PR or SOG also provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG.

    Abstract translation: 基于测量在HSG层的表面之前（W1）和之后（W2）的晶片（其上沉积了HSG的层）的重量的新方法涂覆有光致抗蚀剂或SOG层。 差值ΔW= W2-W1提供HSG沉积层的表面的粗糙度或平滑度的指标。 这种新方法也可以基于测量在HSG层的表面已经涂覆有光致抗蚀剂或SOG层之后的被拒绝或掉落的PR或SOG的重量W。 拒收或掉落的PR或SOG的重量也提供HSG沉积层的表面的粗糙度或平滑度的指标。

Patent Agency Ranking