公开(公告)号：US09389957B2

公开(公告)日：2016-07-12

申请号：US14162914

申请日：2014-01-24

Applicant: Kabushiki Kaisha Toshiba

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Osamu Torii

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1072

Abstract: According to one embodiment, a memory controller that controls non-volatile memory including a data area and a parity area in which parity for data of a fixed length to be stored in the data area is stored, the memory controller including a coding unit configured to generate parity for each of two or more partial data, each of which has a length less than the fixed length, and the memory controller writing one of the parity generated by the coding unit onto the parity area as first parity, writing the partial data and second parity that is the parity, other than the first parity, generated by the coding unit, onto the data area as the data of the fixed length, and writing the second parity onto a position subsequent to the partial data corresponding to the second parity.

Abstract translation: 根据一个实施例，一种控制非易失性存储器的存储器控​​制器，包括数据区和奇偶校验区，其中存储要存储在数据区中的固定长度的数据的奇偶校验，存储器控制器包括编码单元， 为每个长度小于固定长度的部分数据生成奇偶校验，并且存储器控制器将由编码单元生成的奇偶校验之一写入奇偶校验区作为第一奇偶校验，写入部分数据和 作为编码单元产生的除了第一奇偶校验之外的奇偶校验的第二奇偶校验作为固定长度的数据存储到数据区上，并将第二奇偶校验写入与对应于第二奇偶校验的部分数据之后的位置。

公开(公告)号：US09075739B2

公开(公告)日：2015-07-07

申请号：US14141246

申请日：2013-12-26

Applicant: Kabushiki Kaisha Toshiba

Inventor： Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii ,  Koji Horisaki ,  Dong Zhang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/37 ,  H03M13/15

CPC classification number: G06F11/10 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/159 ,  H03M13/3715 ,  H03M13/3746

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract translation: 根据一个实施例，存储装置执行最大校正性能为T比特的代码的纠错处理，所述解码装置包括纠错处理器，用于使用能够处理J比特错误的计算装置（J 是等于或大于1且小于T的整数），其中错误数量期望值的初始值被设置为I（I是等于或大于1且小于T的整数），并且执行增量 的误差数量期望值和纠错处理的执行被重复，直到没有检测到错误或者错误数量期望值变为T位为止。

公开(公告)号：US20140108887A1

公开(公告)日：2014-04-17

申请号：US14141246

申请日：2013-12-26

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Toshikatsu HIDA ,  Shinichi Kanno ,  Osamu Torii ,  Koji Horisaki ,  Dong Zhang

IPC: G06F11/10

CPC classification number: G06F11/10 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/159 ,  H03M13/3715 ,  H03M13/3746

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract translation: 根据一个实施例，存储装置执行最大校正性能为T比特的代码的纠错处理，所述解码装置包括纠错处理器，用于使用能够处理J比特错误的计算装置（J 是等于或大于1且小于T的整数），其中错误数量期望值的初始值被设置为I（I是等于或大于1且小于T的整数），并且执行增量 的误差数量期望值和纠错处理的执行被重复，直到没有检测到错误或者错误数量期望值变为T位为止。

公开(公告)号：US09160371B2

公开(公告)日：2015-10-13

申请号：US14193166

申请日：2014-02-28

Applicant: Kabushiki Kaisha Toshiba

Inventor： Naoaki Kokubun ,  Osamu Torii

IPC: H03M13/00 ,  H03M13/15

CPC classification number: H03M13/151 ,  H03M13/1515 ,  H03M13/2918 ,  H03M13/2942

Abstract: According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G1 (x), generate a second parity group from second group data including third and fourth unit data using G1 (x), and generate a third parity group from the first and second group data and the first and second parity groups using G2 (x), a root of which continues form a root of G1 (x). The memory controller writes the first to fourth unit data and the first to third parity groups in different pages of a nonvolatile memory.

Abstract translation: 根据一个实施例，实施例中的存储器控​​制器包括：编码单元，被配置为使用G1（x）从包括第一和第二单元数据的第一组数据生成第一奇偶校验组，从第二组数据生成第二奇偶校验组，所述第二组数据包括第三和 使用G1（x）的第四单位数据，并且使用G2（x）从第一和第二组数据以及第一和第二奇偶校验组生成第三奇偶校验组，其根的长度形成G1（x）的根。 存储器控制器将第一至第四单元数据和第一至第三奇偶校验组写入非易失性存储器的不同页面中。

公开(公告)号：US08924820B2

公开(公告)日：2014-12-30

申请号：US13762820

申请日：2013-02-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tokumasa Hara ,  Osamu Torii

IPC: G11C29/00 ,  H03M13/00 ,  G06F12/02 ,  G06F11/10

CPC classification number: G06F12/0246 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit.

Abstract translation: 根据一个实施例，存储器系统包括非易失性半导体存储器，其包括每个存储3位的存储器单元，将数据写入非易失性半导体存储器的控制单元和为用户数据生成第一奇偶校验的编码单元 存储在第一页面中，存储在第二页面中的用户数据的第二奇偶校验以及存储在第三页面中的用户数据的第三奇偶校验。 将用户数据，第一奇偶校验，第三奇偶校验和第二奇偶校验的一部分通过第一数据编码和第二奇偶校验的一部分写入非易失性半导体存储器，并将第三奇偶校验的一部分写入 通过其中第一页为0位，第二页为2位，第三页为1位的第二数据编码的非易失性半导体存储器。

公开(公告)号：US20170263331A1

公开(公告)日：2017-09-14

申请号：US15068938

申请日：2016-03-14

Applicant: Kabushiki Kaisha Toshiba

Inventor： Juan Shi ,  Hironori Uchikawa ,  Tokumasa Hara ,  Osamu Torii

IPC: G11C29/02 ,  G11C7/00

CPC classification number: G11C29/021 ,  G11C29/42

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non-volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold-voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.

公开(公告)号：US20170262379A1

公开(公告)日：2017-09-14

申请号：US15262324

申请日：2016-09-12

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tokumasa HARA ,  Osamu Torii ,  Kiichi Tachi ,  Susumu Tamon ,  Shigefumi Irieda ,  Juan Shi ,  Hironori Uchikawa ,  Kejen Lin ,  Akira Yamaga

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.

公开(公告)号：US20170187395A1

公开(公告)日：2017-06-29

申请号：US15456994

申请日：2017-03-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Daiki Watanabe ,  Daisuke Fujiwara ,  Kosuke Morinaga ,  Osamu Torii

IPC: H03M13/29 ,  G11C29/52 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/2909 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2927 ,  H03M13/6502

Abstract: According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimension is different from that of the first component code; determine whether the first rewriting process is erroneous correction based on a result of the second decoding process; and when it is determined that the first rewriting process is erroneous correction, perform a counter process which is undoing the first rewriting process based on the recorded first recurrence information.

公开(公告)号：US09043672B2

公开(公告)日：2015-05-26

申请号：US14017809

申请日：2013-09-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Osamu Torii ,  Riki Suzuki ,  Ryo Yamaki ,  Naoaki Kokubun ,  Daisuke Miyashita ,  Kohei Oikawa

IPC: H03M13/00 ,  G06F11/10

CPC classification number: G06F11/1068

Abstract: According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

Abstract translation: 根据一个实施例，存储器控制器包括：第一闪存编码单元，其根据第一方案对用户数据执行闪存编码，以生成用户数据闪存代码; 对所述用户数据闪存代码执行纠错编码处理以生成奇偶校验的编码单元; 第二闪存编码单元，其根据第二方案对奇偶校验执行闪存编码以产生奇偶校验闪存代码; 以及将用户数据闪存代码和奇偶校验闪存代码写入非易失性存储器的存储器I / F。

公开(公告)号：US20140245101A1

公开(公告)日：2014-08-28

申请号：US13956824

申请日：2013-08-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tokumasa HARA ,  Osamu Torii ,  Yasukazu Kosaki

IPC: H03M13/29

CPC classification number: H03M13/2927 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906

Abstract: According to one embodiment, a semiconductor memory includes a memory cell unit, an encoding circuit that generates a first parity and a second parity for data, and a decoding circuit that performs error correction by using the data, the first parity, and the second parity, the first parity is generated by using a first generation polynomial for the data, the second parity is generated by using a second generation polynomial for the input data and the first parity, the second generation polynomial is selected based on the first generation polynomial, the data and the first parity is output to the outside, and the second parity is not output to the outside.

Abstract translation: 根据一个实施例，半导体存储器包括存储单元单元，产生数据的第一奇偶校验和第二奇偶校验的编码电路，以及通过使用数据，第一奇偶校验和第二奇偶校验执行纠错的解码电路 通过对于数据使用第一代多项式来生成第一奇偶校验，通过使用用于输入数据和第一奇偶校验的第二代多项式来生成第二奇偶校验，基于第一代多项式选择第二代多项式， 数据并将第一奇偶校验输出到外部，并且第二奇偶校验不输出到外部。