公开(公告)号：US5006917A

公开(公告)日：1991-04-09

申请号：US398799

申请日：1989-08-25

Applicant: Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

Inventor： Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

IPC: B23K20/02 ,  B23K20/233 ,  B23K33/00 ,  H01L21/60 ,  H01L21/603

CPC classification number: H01L24/80 ,  B23K20/023 ,  B23K20/233 ,  B23K33/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14

Abstract: A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.cm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separate independently powered anodes, is provided.

公开(公告)号：US07196016B2

公开(公告)日：2007-03-27

申请号：US10675203

申请日：2003-09-29

Applicant: Nicholas I. Buchan ,  Timothy C. Reiley

Inventor： Nicholas I. Buchan ,  Timothy C. Reiley

IPC: H01L21/302

CPC classification number: G11B5/3173 ,  G11B5/102

Abstract: A method for fabricating recording head sliders made from silicon substrates, is described. A Silicon wafer with a SiO2 overcoat is provided, and a layer of material which is resistant to Deep Reactive Ion Etching (DRIE) is deposited on the SiO2 overcoat. A patterned layer of material which is resistant to Reactive Ion Etching (RIE) is deposited on the layer of DRIE-resistant material to form a primary mask. RIE is used through the primary mask to pattern the SiO2 overcoat layer and the layer of DRIE-resistant material. The primary mask is then removing to expose the layer of DRIE-resistant material which has now been patterned to form a secondary mask. DRIE is then used through the secondary mask to cut the Si wafer into pieces. Finally, the secondary mask is removed.

Abstract translation: 描述了由硅衬底制造记录头滑块的方法。 提供具有SiO 2 2外涂层的硅晶片，并且将耐深度反应离子蚀刻（DRIE）的材料层沉积在SiO 2外涂层上。 耐反应离子蚀刻（RIE）的图案化材料层沉积在抗DRIE材料层上以形成初级掩模。 RIE通过初级掩模使用以对SiO 2外涂层和DRIE抗性材料层进行图案化。 然后去除主要掩模以暴露现在被图案化以形成二次掩模的耐DRIE材料层。 然后通过二次掩模使用DRIE将Si晶片切成片。 最后，二次掩模被去除。

公开(公告)号：US06643087B1

公开(公告)日：2003-11-04

申请号：US09519142

申请日：2000-03-06

Applicant: Kenji Kuroki ,  Thomas R. Albrecht ,  Fuminori Sai ,  Yuzo Nakagawa ,  Nobuhisa Koide ,  Masashi Murai ,  Keishi Takahashi ,  Timothy C. Reiley ,  Erno H. Klassen

Inventor： Kenji Kuroki ,  Thomas R. Albrecht ,  Fuminori Sai ,  Yuzo Nakagawa ,  Nobuhisa Koide ,  Masashi Murai ,  Keishi Takahashi ,  Timothy C. Reiley ,  Erno H. Klassen

IPC: G11B2102

CPC classification number: G11B21/12 ,  G11B19/04

Abstract: A method and apparatus to provide a retract circuit that can correspond to the tendency toward miniaturization and low supply voltage. When drive supply voltage Vcc is applied, a retract circuit charges a retract condenser Cr with boosted voltage Vup, equal to three times Vcc, generated by a booster circuit. Then, if the drive supply voltage Vcc is cut off and a VCM driver stops, the retract circuit detects power-off with a power OFF sense circuit, and provides retract delay time by a retract delay circuit. Furthermore, when the retract delay time elapses after the drive power supply is turned off, the retract driver switches the switching circuits on, discharges the retract condenser, charged at the boosted voltage, supplies discharge current to a voice coil, and retracts the head assembly.

Abstract translation: 一种提供可以对应于小型化和低电源电压趋势的缩回电路的方法和装置。 当施加驱动电源电压Vcc时，后退电路对由升压电路产生的升压电压Vup等于三倍Vcc充电回缩电容器Cr。 然后，如果驱动器电源电压Vcc被切断并且VCM驱动器停止，则缩回电路用电源OFF感测电路检测掉电，并且通过缩回延迟电路提供缩回延迟时间。 此外，当在驱动电源关闭之后经过缩回延迟时间时，后退驱动器接通开关电路，放电收缩冷凝器，以升压电压充电，向扬声器提供放电电流，并使头部组件 。

公开(公告)号：US06556380B2

公开(公告)日：2003-04-29

申请号：US09835722

申请日：2001-04-10

Applicant: Richard Bunch ,  Linden J. Crawforth ,  Anthony A. Razouk ,  Timothy C. Reiley

Inventor： Richard Bunch ,  Linden J. Crawforth ,  Anthony A. Razouk ,  Timothy C. Reiley

IPC: G11B5187

CPC classification number: G11B5/6005

Abstract: A trapezoidal shaped silicon slider is described in the present invention. The slider has a first parallel surface larger than a second parallel surface, thereby generating a built-in positive pitch with respect to a recording medium when the slider is incorporated into a hard disk drive. The slider further includes round edges at the first parallel surface, longitudinal holes within its body, non-planar slanted side surfaces, and a rounded leading edge. The silicon, trapezoidal slider is fabricated using a deep reactive ion etching (DRIE) technique.

公开(公告)号：US5135155A

公开(公告)日：1992-08-04

申请号：US664359

申请日：1991-03-04

Applicant: Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

Inventor： Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

IPC: B23K20/02 ,  B23K20/233 ,  B23K33/00 ,  H01L21/603

CPC classification number: H01L24/80 ,  B23K20/023 ,  B23K20/233 ,  B23K33/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14

Abstract: A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.mm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separate independently powered anodes, is provided.

公开(公告)号：US4862322A

公开(公告)日：1989-08-29

申请号：US188805

申请日：1988-05-02

Applicant: Harry R. Bickford ,  Mark F. Bregman ,  Paul A. Moskowitz ,  Michael J. Palmer ,  Timothy C. Reiley ,  Paige A. Poore ,  Caroline A. Kovac

Inventor： Harry R. Bickford ,  Mark F. Bregman ,  Paul A. Moskowitz ,  Michael J. Palmer ,  Timothy C. Reiley ,  Paige A. Poore ,  Caroline A. Kovac

IPC: H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L23/49575 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/06513 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107

Abstract: An integrated circuit device package in which integrated circuit devices are mounted with active faces placed facing each other to form a double-device structure. Input/output terminals on the active faces of each device can be electrically interconnected by placing an interconnection means between the chips to electrically interconnect input/output terminals on the active faces of the first and second device. Beam leads, each having an inner and outer lead bond site, project outwardly from between the devices where each of the inner lead bond site is solderlessly bonded between conducting patterns on each device bonded. A series of double-device structures can be formed on a tape having a plurality of sets of beam lead patterns thereon. Each beam lead of each set having an inner and outer lead bond site, projects outwardly from between the double-device structure, the inner lead bond site being solderlessly bonded between conducting patterns on each device.

公开(公告)号：US06802761B1

公开(公告)日：2004-10-12

申请号：US10392630

申请日：2003-03-20

Applicant: Jacey R. Beaucage ,  Timothy C. Reiley ,  Huey-Ming Tzeng ,  Xiao Z. Wu

Inventor： Jacey R. Beaucage ,  Timothy C. Reiley ,  Huey-Ming Tzeng ,  Xiao Z. Wu

IPC: B24B100

CPC classification number: B24B37/16 ,  B24D18/00

Abstract: A lapping plate has photolithographically defined patterns that are electroplated to produce lands with well-defined channels. By choosing a particular geometry, the retention force is significantly reduced over prior art options, while still retaining a high land area fraction. In some versions, the material is electroplated onto sufficiently thin substrates to allow conformation to a curved vacuum chuck. This configuration provides a very large reduction in retraction force when compared to smooth, flat lapping plates. In addition, the substrate used to form the lapping plate has reduced thickness, and a vacuum chuck is used to pull the thin, flat lapping plate against it to define the curvature. This allows the lapping plate to be charged by a flat charging ring. The substrate used is typically glass and has been sputter-metallized on both sides. The resist is then patterned, leaving an exposed pattern in the metallization on both sides.

Abstract translation: 研磨板具有光刻定义的图案，其电镀以产生具有明确定义的通道的焊盘。 通过选择特定的几何形状，保持力比现有技术的选择显着降低，同时仍然保持高的陆地面积分数。 在一些版本中，将材料电镀到足够薄的衬底上以允许构成弯曲的真空吸盘。 与平滑的平板研磨板相比，该构造提供了非常大的缩回力的减小。 此外，用于形成研磨板的基底具有减小的厚度，并且使用真空卡盘将薄的平的研磨板拉向其以限定曲率。 这样可以通过一个扁平的充电环来对研磨板进行充电。 所使用的基底通常是玻璃并且已经在两侧溅射金属化。 然后将抗蚀剂图案化，在两侧的金属化中留下暴露的图案。

公开(公告)号：US5189363A

公开(公告)日：1993-02-23

申请号：US583261

申请日：1990-09-14

Applicant: Mark F. Bregman ,  Paul R. Hoffman ,  Peter G. Ledermann ,  Paul A. Moskowitz ,  Roger A. Pollak ,  Timothy C. Reiley ,  Mark B. Ritter

Inventor： Mark F. Bregman ,  Paul R. Hoffman ,  Peter G. Ledermann ,  Paul A. Moskowitz ,  Roger A. Pollak ,  Timothy C. Reiley ,  Mark B. Ritter

IPC: G01R31/26 ,  G01R1/073

CPC classification number: G01R1/0735

Abstract: A system for testing chips uses a patterned tape having a patterned array of cantilevered contact leads. The tape serves as an interface between the chip under test and a testing unit by providing conductive leads from the I/O terminals on the chip to an off-chip measuring system. The leads on the array may have balls, tips or other shapes on the end to provide contact with the terminals and compensate for height differences. The tape is a single frame or has a series of arrays each positioned around an opening where the chip will be located when a particular pattern is positioned over that chip for test. The pattern on the tape may be the same array or a different array. The tape is indexed to a new pattern when the old one is damaged or no longer needed. Alignment with the chip is by optical sensing and physical pin movement. The tape may have a flap protruding into an aperture and deflectable to provide for planar contact of the leads to the device under test.

公开(公告)号：US5120418A

公开(公告)日：1992-06-09

申请号：US664388

申请日：1991-03-04

Applicant: Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

Inventor： Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

IPC: B23K20/02 ,  B23K20/233 ,  B23K33/00 ,  H01L21/603

CPC classification number: H01L24/80 ,  B23K20/023 ,  B23K20/233 ,  B23K33/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14

Abstract: A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.cm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separatre independently powered anodes, is provided.

Abstract translation: 用于集成电路封装中的热压接的接触构件在导体端具有均匀的织构可变形层，硬度值在Knoop尺度上大约为90的软金的范围内，粗糙的表面形态具有大约 1微米调制频率和脊之间的深度为平均集成电路板的1/4至1/2。 可变形层通过在0.03-0.05mA / sq.cm范围内的强电负电镀浴中镀金而制成。 当前密度。 提供了用于电镀不同区域的电镀装置，具有不同的电负性条件，具有独立供电的阳极。

公开(公告)号：US5028983A

公开(公告)日：1991-07-02

申请号：US263835

申请日：1988-10-27

Applicant: Harry R. Bickford ,  Mark F. Bregman ,  Thomas M. Cipolla ,  John Gow, III ,  Peter G. Ledermann ,  Ekkehard F. Miersch ,  Leonard T. Olson ,  David P. Pagnani ,  Timothy C. Reiley ,  Uh-Po E. Tsou ,  Walter V. Vilkelis

Inventor： Harry R. Bickford ,  Mark F. Bregman ,  Thomas M. Cipolla ,  John Gow, III ,  Peter G. Ledermann ,  Ekkehard F. Miersch ,  Leonard T. Olson ,  David P. Pagnani ,  Timothy C. Reiley ,  Uh-Po E. Tsou ,  Walter V. Vilkelis

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L24/50 ,  H01L23/49572 ,  H01L23/49861 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011

Abstract: Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.