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公开(公告)号：US20190052279A1
公开(公告)日：2019-02-14
申请号：US16077087
申请日：2017-01-24
Applicant: Intel IP Corporation
Inventor： Elan Banin , Tamar Marom , Gil Horovitz , Rotem Banin
IPC: H03L7/091
Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.
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公开(公告)号：US10181856B2
公开(公告)日：2019-01-15
申请号：US15395504
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
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公开(公告)号：US20180091177A1
公开(公告)日：2018-03-29
申请号：US15274509
申请日：2016-09-23
Applicant: Intel IP Corporation
Inventor： Elan Banin , Uri Parker , Ofir Degani , Michael Kerner
CPC classification number: H04B1/0475 , H04B2001/0425 , H04L27/367
Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.
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公开(公告)号：US09231602B1
公开(公告)日：2016-01-05
申请号：US14490115
申请日：2014-09-18
Applicant: Intel IP Corporation
Inventor： Elan Banin , Rotem Banin , Ofir Degani , Ran Shimon , Ashoke Ravi
CPC classification number: G04F10/005 , H03L7/085 , H03L2207/50
Abstract: A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.
Abstract translation: 数字锁相环用时间数字转换器和估计与时间数字转换器的量化输出相关联的未量化相位的先验概率相位估计分量或估计器分量进行操作。 时间 - 数字转换器产生量化值作为本地振荡器的本地振荡器信号和参考时钟的参考信号的量化输出。 估计分量从作为与时间 - 数字转换器相关的先验数据和量化值的边界的函数的量化值估计相位值。
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Patent Agency Ranking
公开(公告)号：US10768580B2
公开(公告)日：2020-09-08
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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公开(公告)号：US10680619B2
公开(公告)日：2020-06-09
申请号：US16170716
申请日：2018-10-25
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
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公开(公告)号：US20190384230A1
公开(公告)日：2019-12-19
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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公开(公告)号：US20190068200A1
公开(公告)日：2019-02-28
申请号：US16170716
申请日：2018-10-25
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
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公开(公告)号：US09923563B1
公开(公告)日：2018-03-20
申请号：US15389520
申请日：2016-12-23
Applicant: Intel IP Corporation
Inventor： Gil Horovitz , Elan Banin , Igal Kushnir , Aryeh Farber , Ran Krichman , Ofir Degani , Rotem Banin
IPC: H03L7/08
CPC classification number: H03L7/08 , H03K5/1565 , H03L7/0805 , H03L7/085 , H03L2207/10
Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.
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