公开(公告)号：US20180095923A1

公开(公告)日：2018-04-05

申请号：US15283309

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4265 ,  G11C27/04

Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

公开(公告)号：US11586579B2

公开(公告)日：2023-02-21

申请号：US17513795

申请日：2021-10-28

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US11354264B2

公开(公告)日：2022-06-07

申请号：US17184737

申请日：2021-02-25

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US10152446B2

公开(公告)日：2018-12-11

申请号：US15283309

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

IPC: G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G11C27/04

Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

公开(公告)号：US10025746B2

公开(公告)日：2018-07-17

申请号：US14578395

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： William R. Halleck ,  Rahul Shah ,  Venkatraman Iyer

IPC: G06F13/42 ,  G06F13/22

Abstract: A signal is received, a boundary of which is to be sent in alignment with a sync counter value. A nominal latency of a link is determined based on the sync counter value. Additional latency is applied to the signal to increase the nominal latency to a target latency for the link.

公开(公告)号：US09910809B2

公开(公告)日：2018-03-06

申请号：US14578175

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： William R. Halleck ,  Rahul Shah ,  Venkatraman Iyer

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/124 ,  G06F13/1678 ,  G06F13/4282

Abstract: A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent over one or more lanes of a link and is to include at least a portion of a start of data sequence (SDS) to include a predefined sequence and a byte number value. The byte number value is to indicate a number of bytes measured from a preceding control interval.

公开(公告)号：US11294852B2

公开(公告)日：2022-04-05

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20210182231A1

公开(公告)日：2021-06-17

申请号：US17184737

申请日：2021-02-25

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US10963415B2

公开(公告)日：2021-03-30

申请号：US16802209

申请日：2020-02-26

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US10931329B2

公开(公告)日：2021-02-23

申请号：US15394278

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Rahul R. Shah ,  William R. Halleck ,  Fulvio Spagna ,  Venkatraman Iyer

IPC: H04L12/407 ,  H04B3/36 ,  H04L12/933 ,  H04L12/803 ,  G06F13/40

Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.