公开(公告)号：US11222119B2

公开(公告)日：2022-01-11

申请号：US16392863

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ron Story ,  Mahesh Natu

IPC: G06F9/04 ,  G06F21/57 ,  G06F9/455 ,  G06F9/448 ,  G06F9/4401

Abstract: Technologies for secure native code invocation include a computing device having an operating system and a firmware environment. The operating system executes a firmware method in an operating system context using a virtual machine. In response to invoking the firmware method, the operating system invokes a callback to a bridge driver in the operating system context. In response to the callback, the bridge driver invokes a firmware runtime service in the operating system context. The firmware environment executes a native code handler in the operating system context in response to invoking the firmware runtime service. The native code handler may be executed in a de-privileged container. The firmware method may process results data stored in a firmware mailbox by the native code handler, which may include accessing a hardware resource using a firmware operation region.

公开(公告)号：US11068339B2

公开(公告)日：2021-07-20

申请号：US16417555

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US10445154B2

公开(公告)日：2019-10-15

申请号：US15435444

申请日：2017-02-17

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Vincent J. Zimmer ,  Rajesh Poornachandran

IPC: G06F9/54

Abstract: This disclosure is directed to firmware-related event notification. A device may comprise an operating system (OS) configured to operate on a platform. During initialization of the device a firmware module in the platform may load at least one globally unique identifier (GUID) into a firmware configuration table. When the platform notifies the OS, the firmware module may load at least one GUID into a platform notification table and may set a platform notification bit in a platform notification table status field. Upon detecting the notification, an OS management module may establish a source of the notification by querying the platform notification table. The platform notification bit may cause the OS management module to compare GUIDs in the platform notification table and the firmware configuration table. Services may be called based on any matching GUIDs. If no GUIDs match, the services may be called based on firmware variables in the device.

公开(公告)号：US20190272214A1

公开(公告)日：2019-09-05

申请号：US16417555

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US09612887B2

公开(公告)日：2017-04-04

申请号：US14751733

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Vincent J. Zimmer ,  Rajesh Poornachandran

IPC: G06F9/54

CPC classification number: G06F9/544 ,  G06F9/542

Abstract: This disclosure is directed to firmware-related event notification. A device may comprise an operating system (OS) configured to operate on a platform. During initialization of the device a firmware module in the platform may load at least one globally unique identifier (GUID) into a firmware configuration table. When the platform notifies the OS, the firmware module may load at least one GUID into a platform notification table and may set a platform notification bit in a platform notification table status field. Upon detecting the notification, an OS management module may establish a source of the notification by querying the platform notification table. The platform notification bit may cause the OS management module to compare GUIDs in the platform notification table and the firmware configuration table. Services may be called based on any matching GUIDs. If no GUIDs match, the services may be called based on firmware variables in the device.

公开(公告)号：US09454380B2

公开(公告)日：2016-09-27

申请号：US13977593

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Jose Andy Vargas

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/44 ,  G06F17/30 ,  G06F9/445 ,  G06F1/28 ,  G06F11/36 ,  G06F1/26 ,  G06F9/22 ,  G06F11/34 ,  G06F9/30 ,  G06F1/20 ,  G06F15/78 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F17/30339 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS RAS services for one or more hardware components, regardless of a particular platform hardware configuration, as long as the platform hardware and OS are in conformance with the PPM interface.

Abstract translation: 在一些实施例中，只要平台硬件和OS与PPM接口一致，可以向PPM接口提供功能，以便于针对一个或多个硬件组件的OS RAS服务，而不管特定的平台硬件配置。

公开(公告)号：US12008359B2

公开(公告)日：2024-06-11

申请号：US16790488

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Michael A. Rothman

IPC: G06F8/656 ,  G06F9/4401 ,  G06F21/57

CPC classification number: G06F8/656 ,  G06F9/4401 ,  G06F21/572 ,  G06F2221/033

Abstract: Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.

公开(公告)号：US11941391B2

公开(公告)日：2024-03-26

申请号：US16841410

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Sarathy Jayakumar ,  Chuan Song ,  Ruixia Li ,  Xiaojin Yuan ,  Haiyue Wang ,  Chong Han

IPC: G06F8/656 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/445 ,  G06F9/455

CPC classification number: G06F8/656 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/44557 ,  G06F9/45541

Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.

公开(公告)号：US20230315575A1

公开(公告)日：2023-10-05

申请号：US17711465

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Eswar Konduru ,  John Holm

IPC: G06F11/14 ,  G06F9/445 ,  G06F21/57

CPC classification number: G06F11/142 ,  G06F9/445 ,  G06F21/572 ,  G06F2221/033 ,  G06F2201/805

Abstract: Techniques and mechanisms for supporting machine check functionality with a handler which is implemented in firmware. In an embodiment, a processor executes first firmware code to implement a machine check event (MCE) detector. The MCE detector detects a hardware error of a platform which includes the processor, and generates a call to invoke an MCE handler which the processor implements by executing second firmware code. The MCE handler is called, outside of a software context, to attempt a recovery from the hardware error. The call is performed independent of any system management interrupt being based on the detected hardware error. In another embodiment, another MCE handler of an operating system is conditionally invoked where it is determined that the attempted recovery by the first MCE handler was unsuccessful.

公开(公告)号：US20230169171A1

公开(公告)日：2023-06-01

申请号：US17996936

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Zijian You

IPC: G06F21/57 ,  G06F21/54

CPC classification number: G06F21/572 ,  G06F21/54 ,  G06F21/575

Abstract: Systems, apparatuses and methods may provide technology for managing BIOS modules. The technology may include a boot controller to perform a boot procedure by loading and executing a basic input output system (BIOS) boot module, a setup controller to load and execute a BIOS boot module during runtime (i.e., bypassing reboot) using a changed hardware configuration parameter, and an update controller to load and execute a new or updated BIOS boot module during runtime (i.e., bypassing reboot), where each controller is to operate under direction of an operating system (OS). The technology may perform these BIOS operations within a secure BIOS environment.