公开(公告)号：US11789889B2

公开(公告)日：2023-10-17

申请号：US17557837

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Mahesh Natu

IPC: H04L12/40 ,  G06F13/42

CPC classification number: G06F13/4221 ,  H04L12/40097

Abstract: Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.

公开(公告)号：US11216404B2

公开(公告)日：2022-01-04

申请号：US16673259

申请日：2019-11-04

Applicant: Intel Corporation

Inventor： Mahesh Natu

IPC: G06F13/42 ,  H04L12/40

Abstract: Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.

公开(公告)号：US20210312044A1

公开(公告)日：2021-10-07

申请号：US17354125

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Michael Berger ,  Xiaoyu Ruan ,  Purushottam Goel ,  Mahesh Natu ,  Bharat Pillilli

IPC: G06F21/55 ,  G06F21/57

Abstract: An apparatus comprising a computer platform, including a central processing unit (CPU) comprising a first security engine to perform security operations at the CPU and a chipset comprising a second security engine to perform security operations at the chipset, wherein the first security engine and the second security engine establish a secure channel session between the CPU and the chipset to secure data transmitted between the CPU and the chipset.

公开(公告)号：US20200065290A1

公开(公告)日：2020-02-27

申请号：US16673259

申请日：2019-11-04

Applicant: Intel Corporation

Inventor： Mahesh Natu

IPC: G06F13/42 ,  H04L12/40

Abstract: Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.

公开(公告)号：US10922161B2

公开(公告)日：2021-02-16

申请号：US16203578

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Bryan White ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Mahesh Natu

IPC: G06F11/00 ,  G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US20170010991A1

公开(公告)日：2017-01-12

申请号：US15270151

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

IPC: G06F13/24 ,  G11C7/10 ,  G11C11/406

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的体系结构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。

公开(公告)号：US09465647B2

公开(公告)日：2016-10-11

申请号：US14048451

申请日：2013-10-08

Applicant: INTEL CORPORATION

Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

IPC: G06F9/48 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。

公开(公告)号：US11741227B2

公开(公告)日：2023-08-29

申请号：US17354125

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Michael Berger ,  Xiaoyu Ruan ,  Purushottam Goel ,  Mahesh Natu ,  Bharat Pillilli

IPC: G06F21/55 ,  G06F21/57

CPC classification number: G06F21/556 ,  G06F21/554 ,  G06F21/572

Abstract: An apparatus comprising a computer platform, including a central processing unit (CPU) comprising a first security engine to perform security operations at the CPU and a chipset comprising a second security engine to perform security operations at the chipset, wherein the first security engine and the second security engine establish a secure channel session between the CPU and the chipset to secure data transmitted between the CPU and the chipset.

公开(公告)号：US20230123174A1

公开(公告)日：2023-04-20

申请号：US17973990

申请日：2022-10-26

Applicant: Intel Corporation

Inventor： Mahesh Natu ,  Adrian Pearson

IPC: H04L9/06 ,  G06F13/40 ,  G06F8/70 ,  G06F21/62 ,  G06F21/57 ,  H04L9/32

Abstract: Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express - PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.

公开(公告)号：US11522679B2

公开(公告)日：2022-12-06

申请号：US15836225

申请日：2017-12-08

Applicant: Intel Corporation

Inventor： Mahesh Natu ,  Adrian Pearson

IPC: H04L9/06 ,  G06F13/40 ,  G06F8/70 ,  G06F21/62 ,  G06F21/57 ,  H04L9/32

Abstract: Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express—PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.