公开(公告)号：US20200210178A1

公开(公告)日：2020-07-02

申请号：US16811242

申请日：2020-03-06

申请人： Intel Corporation

发明人： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC分类号： G06F9/30

摘要： A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.

公开(公告)号：US10216616B2

公开(公告)日：2019-02-26

申请号：US15201405

申请日：2016-07-02

申请人： Intel Corporation

发明人： Beeman C. Strong ,  Matthew C. Merten ,  Lee W. Baugh

IPC分类号： G06F11/36 ,  G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F11/34

摘要： A processor is disclosed and comprises a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.

公开(公告)号：US20190050566A1

公开(公告)日：2019-02-14

申请号：US15966358

申请日：2018-04-30

申请人： Intel Corporation

发明人： Michael LeMay ,  Ravi L. Sahita ,  Beeman C. Strong ,  Thilo Schmitt ,  Yuriy Bulygin ,  Markus T. Metzger

IPC分类号： G06F21/56 ,  G06F21/52 ,  G06F21/44

摘要： Technologies for control flow exploit mitigation include a computing device having a processor with real-time instruction tracing support. During execution of a process, the processor generates trace data indicative of control flow of the process. The computing device analyzes the trace data to identify suspected control flow exploits. The computing device may use heuristic algorithms to identify return-oriented programming exploits. The computing device may maintain a shadow stack based on the trace data. The computing device may identify indirect branches to unauthorized addresses based on the trace data to identify jump-oriented programming exploits. The computing device may check the trace data whenever the process is preempted. The processor may detect mispredicted return instructions in real time and invoke a software handler in the process space of the process to verify and maintain the shadow stack. Other embodiments are described and claimed.

公开(公告)号：US09965375B2

公开(公告)日：2018-05-08

申请号：US15194881

申请日：2016-06-28

申请人： INTEL CORPORATION

发明人： Matthew C. Merten ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Grant G. Zhou ,  Andreas Kleen ,  Kimberly C. Weier ,  Angela D. Schmid ,  Stanislav Bratanov ,  Seth Abraham ,  Jason W. Brandt ,  Ahmad Yasin

IPC分类号： G06F11/36 ,  G06F9/455 ,  H04L12/26 ,  H04L12/24

CPC分类号： G06F11/3636 ,  G06F9/45558 ,  G06F2009/45591 ,  H04L41/0613 ,  H04L43/04

摘要： A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.

公开(公告)号：US09910475B2

公开(公告)日：2018-03-06

申请号：US14580553

申请日：2014-12-23

申请人： Intel Corporation

发明人： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC分类号： G06F1/32 ,  G06F11/30 ,  G06F11/34

CPC分类号： G06F1/3206 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/348 ,  G06F2201/86

摘要： A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US09716646B2

公开(公告)日：2017-07-25

申请号：US14334071

申请日：2014-07-17

申请人： Intel Corporation

发明人： Tsvika Kurts ,  Beeman C. Strong ,  Ofer Levy ,  Gabi Malka ,  Zeev Sperber

IPC分类号： H04L7/00 ,  H04L12/26 ,  H04J3/06

CPC分类号： H04L43/50 ,  H04J3/0664 ,  H04L43/106

摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

公开(公告)号：US10656697B2

公开(公告)日：2020-05-19

申请号：US15911577

申请日：2018-03-05

申请人： Intel Corporation

发明人： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC分类号： G06F1/32 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3206

摘要： A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US10592244B2

公开(公告)日：2020-03-17

申请号：US15423143

申请日：2017-02-02

申请人： INTEL CORPORATION

发明人： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC分类号： G06F9/30

摘要： An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.

公开(公告)号：US10346167B2

公开(公告)日：2019-07-09

申请号：US15384300

申请日：2016-12-19

申请人： INTEL CORPORATION

发明人： Toby Opferman ,  James B. Crossland ,  Jason W. Brandt ,  Beeman C. Strong

IPC分类号： G06F11/00 ,  G06F9/30 ,  G06F11/34 ,  G06F11/36 ,  G06F9/38 ,  G06F11/30

摘要： Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

公开(公告)号：US20190050041A1

公开(公告)日：2019-02-14

申请号：US15911577

申请日：2018-03-05

申请人： Intel Corporation

发明人： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC分类号： G06F1/32 ,  G06F11/34 ,  G06F11/30

摘要： A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.