公开(公告)号：US08822141B1

公开(公告)日：2014-09-02

申请号：US13785816

申请日：2013-03-05

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Kevin S. Petrarca ,  Stuart A. Sieg

IPC: G03F7/20

CPC classification number: H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for printing a wafer ID on a wafer, the method comprises identifying a wafer ID on a back side of the wafer. Subsequently, etching a plurality of recesses, consistent in size with chip features of the wafer, into the front side of the wafer, such that the plurality of recesses depicts the wafer ID. The method further comprises filling the recesses with a metal.

Abstract translation: 一种用于在晶片上印刷晶片ID的方法，所述方法包括在晶片的背面识别晶片ID。 随后，将与晶片的芯片特征尺寸一致的多个凹槽蚀刻到晶片的前侧，使得多个凹槽示出晶片ID。 该方法还包括用金属填充凹部。

公开(公告)号：US11183389B2

公开(公告)日：2021-11-23

申请号：US16353641

申请日：2019-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wenyu Xu ,  Stuart A. Sieg ,  Ruilong Xie ,  John R. Sporre

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/3213

Abstract: A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

公开(公告)号：US10985025B2

公开(公告)日：2021-04-20

申请号：US16173331

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66

Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US10832919B2

公开(公告)日：2020-11-10

申请号：US15950628

申请日：2018-04-11

Applicant: International Business Machines Corporation

Inventor： Romain Lallement ,  Stuart A. Sieg

IPC: G06G7/48 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/66 ,  G06F30/20 ,  G06F111/20

Abstract: A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.

公开(公告)号：US10811507B2

公开(公告)日：2020-10-20

申请号：US15709902

申请日：2017-09-20

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Fee Li Lie ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L27/02 ,  H01L21/8234

Abstract: Embodiments of the invention are directed to configurations of semiconductor devices. A non-limiting example configuration includes a plurality of first transistors formed over a performance region of a major surface of a substrate. Each of the plurality of first transistors includes a first channel fin structure and a first gate structure along at least a portion of a sidewall surface of the first channel fin structure. The first gate structure includes a first gate thickness dimension. A plurality of second transistors is formed over a density region of the major surface of the substrate. Each of the plurality of second transistors includes a second channel fin structure and a second gate structure along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

公开(公告)号：US20200135570A1

公开(公告)日：2020-04-30

申请号：US16173378

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/033 ,  H01L27/088 ,  H01L29/66

Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US20190371613A1

公开(公告)日：2019-12-05

申请号：US16000485

申请日：2018-06-05

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Ekmini A. De Silva ,  Stuart A. Sieg ,  Eric Miller

IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

公开(公告)号：US10410875B2

公开(公告)日：2019-09-10

申请号：US15802634

申请日：2017-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean D. Burns ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A. M. Mignot ,  Stuart A. Sieg

IPC: H01L21/308 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/033

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

公开(公告)号：US20190243927A1

公开(公告)日：2019-08-08

申请号：US15889415

申请日：2018-02-06

Applicant: International Business Machines Corporation

Inventor： Romain Lallement ,  Stuart A. Sieg

IPC: G06F17/50 ,  H01L21/3105

CPC classification number: G06F17/504 ,  H01L21/31058 ,  H01L29/66666 ,  H01L29/66795

Abstract: Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.

公开(公告)号：US20180350600A1

公开(公告)日：2018-12-06

申请号：US16058088

申请日：2018-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Anuja E. DeSilva ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A.M. Mignot ,  Stuart A. Sieg

IPC: H01L21/033 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.