公开(公告)号：US08943365B2

公开(公告)日：2015-01-27

申请号：US14042975

申请日：2013-10-01

Applicant: International Business Machines Corporation

Inventor： Sascha Junghans ,  Andreas Koenig

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0793

Abstract: A computer program product for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Abstract translation: 一种用于处理第一通信装置和第二通信装置之间的通信链路问题的计算机程序产品。 使用通信链路在第一通信装置和第二通信装置之间传送数据信号，控制信号和/或错误信息。 该方法包括：响应于检测到的通信链路问题，激活表示错误信息的第一通信装置中的静态识别模式，以及停止第一通信装置内部的时钟信号（Clk）以冻结当前错误状况，并传送 使用通信链路将激活的静态识别模式永久地和/或重复地发送到第二通信装置。

公开(公告)号：US20140032983A1

公开(公告)日：2014-01-30

申请号：US14042975

申请日：2013-10-01

Applicant: International Business Machines Corporation

Inventor： Sascha Junghans ,  Andreas Koenig

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0793

Abstract: A computer program product for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Abstract translation: 一种用于处理第一通信装置和第二通信装置之间的通信链路问题的计算机程序产品。 使用通信链路在第一通信装置和第二通信装置之间传送数据信号，控制信号和/或错误信息。 该方法包括：响应于检测到的通信链路问题，激活表示错误信息的第一通信装置中的静态识别模式，以及停止第一通信装置内部的时钟信号（Clk）以冻结当前错误状况，并传送 使用通信链路将激活的静态识别模式永久地和/或重复地发送到第二通信装置。

公开(公告)号：US10353833B2

公开(公告)日：2019-07-16

申请号：US15646340

申请日：2017-07-11

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish G. Kurup

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

公开(公告)号：US10223308B2

公开(公告)日：2019-03-05

申请号：US15808071

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Sascha Junghans ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F13/42 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/1027

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

公开(公告)号：US20190018804A1

公开(公告)日：2019-01-17

申请号：US15806407

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish Kurup

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/1626 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4013 ,  G06F13/42

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

公开(公告)号：US20190018803A1

公开(公告)日：2019-01-17

申请号：US15646340

申请日：2017-07-11

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish Kurup

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F13/1626 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4013 ,  G06F13/42

Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

公开(公告)号：US10169272B2

公开(公告)日：2019-01-01

申请号：US14827636

申请日：2015-08-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Jeorg Walter

IPC: G06F13/28 ,  G06F13/38 ,  G06F12/0862 ,  G06F12/084 ,  G06F3/06

Abstract: A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.

公开(公告)号：US20180365182A1

公开(公告)日：2018-12-20

申请号：US15808071

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Sascha Junghans ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F13/4282

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

公开(公告)号：US10007625B2

公开(公告)日：2018-06-26

申请号：US14927055

申请日：2015-10-29

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/36 ,  G06F13/00 ,  G06F13/28 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/287 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/4022

Abstract: According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable.

公开(公告)号：US09916268B2

公开(公告)日：2018-03-13

申请号：US14551798

申请日：2014-11-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

IPC: G06F13/28 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0871

CPC classification number: G06F13/28 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/6042

Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.