公开(公告)号：US11347662B2

公开(公告)日：2022-05-31

申请号：US15721777

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1045 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

公开(公告)号：US10817447B2

公开(公告)日：2020-10-27

申请号：US15350998

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Camron B. Rust

IPC: G06F13/28 ,  G06F12/1027 ,  G06F12/1081 ,  G06F9/4401

Abstract: Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.

公开(公告)号：US20160182391A1

公开(公告)日：2016-06-23

申请号：US14578429

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Kevin B. Theobald ,  Rupin H. Vakharwala ,  Robert J. Toepfer ,  Erik G. Hallnor ,  Robert P. Adler

IPC: H04L12/801 ,  H04L12/707 ,  H04L12/46 ,  H04L12/925 ,  H04L12/911

CPC classification number: H04L47/39 ,  H04L12/4641 ,  H04L45/24 ,  H04L47/722 ,  H04L47/726 ,  H04L47/821

Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.

Abstract translation: 提供交通控制逻辑以支持链路上的多个信道。 提供多个保留的信用计数器，每个识别多个通道中相应的一个信道的预留流量控制信用。 此外，提供共享信用计数器以识别要在多个虚拟通道中的两个或更多个之间共享的共享流控制信用。

公开(公告)号：US20230134657A1

公开(公告)日：2023-05-04

申请号：US17519384

申请日：2021-11-04

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Rupin H. Vakharwala

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/54 ,  G06F13/24

Abstract: A system comprises a physical processor to execute a virtual machine manager to run, on a logical core, a virtual machine including a guest user application and a virtual CPU. Circuitry coupled to an external device is to receive an interrupt request from the external device for the guest user application, locate a first interrupt data structure associated with the guest user application, generate a first interrupt with the first interrupt data structure based on a first interrupt vector for the interrupt request, locate a second interrupt data structure associated with the virtual CPU, and generate a first notification interrupt for the virtual CPU with the second interrupt data structure based on a first notification vector in the first interrupt data structure. The circuitry may generate a second notification interrupt for the logical core using a second notification vector and a logical core identifier from the second interrupt data structure.

公开(公告)号：US20220414020A1

公开(公告)日：2022-12-29

申请号：US17899912

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Philip Lantz ,  David J. Harriman

IPC: G06F12/1027 ,  G06F12/0891

Abstract: In an embodiment, a core includes at least one execution circuit. The core may be configured to: send a command for a first address translation cache (ATC) of a first device to perform an operation, the core to send the command to a first device queue of a shared memory, the first device queue associated with the first ATC; and send a register write directly to the first device to inform the first ATC regarding presence of the command in the first device queue. Other embodiments are described and claimed.

公开(公告)号：US20220365887A1

公开(公告)日：2022-11-17

申请号：US17827458

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1045 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

公开(公告)号：US11126554B2

公开(公告)日：2021-09-21

申请号：US16361512

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Paula Petrica

IPC: G06F12/00 ,  G06F12/0862 ,  G06F13/42 ,  G06F12/1036

Abstract: Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a write access to one or more memory address locations specified in the memory address translation request message; identify, from an address translation and protection table (ATPT), a dirty bit value associated with the one or more memory address locations; and transmit a translation of the one or more memory address locations and a read or read+write permission to the device based on the permission indication in the memory address translation request message and the dirty bit.

公开(公告)号：US20180373633A1

公开(公告)日：2018-12-27

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US20180349288A1

公开(公告)日：2018-12-06

申请号：US15608145

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Eric A. Gouldey ,  Camron B. Rust ,  Brett Ireland ,  Rajesh M. Sankaran

IPC: G06F12/1027 ,  G06F12/0862 ,  G06F11/07

CPC classification number: G06F12/1027 ,  G06F11/07 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/305 ,  G06F2212/6028

Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.

公开(公告)号：US20180011651A1

公开(公告)日：2018-01-11

申请号：US15207218

申请日：2016-07-11

Applicant: INTEL CORPORATION

Inventor： Rajesh M. Sankaran ,  Prashant Sethi ,  Asit K. Mallick ,  David Woodhouse ,  Rupin H. Vakharwala

IPC: G06F3/06 ,  G06F12/14

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/064 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/651 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/683

Abstract: An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.