公开(公告)号：US09984003B2

公开(公告)日：2018-05-29

申请号：US15257506

申请日：2016-09-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Licheng Chen ,  Mingyu Chen

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/6042 ,  G06F2212/651 ,  G06F2212/653 ,  G06F2212/657

Abstract: A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

公开(公告)号：US09927860B2

公开(公告)日：2018-03-27

申请号：US14685272

申请日：2015-04-13

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan

IPC: G06F1/32 ,  G06F9/50 ,  G06F12/06 ,  G06F3/06

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/068 ,  G06F9/5016 ,  G06F9/5094 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/251 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154 ,  Y02D10/22 ,  Y02D50/20

Abstract: A method for reducing power consumption of a memory system and a memory controller are provided. The method for reducing power consumption of a memory system includes: determining whether a dynamic random access memory DRAM memory module with a low access frequency exists in a memory system; when a DRAM memory module with a low access frequency exists, transfer, according to a size of a working set in the memory system, page data that does not belong to the working set to a non-volatile memory NVM memory module, where the page data that does not belong to the working set is page data that does not need to be accessed when a process runs within preset time.

公开(公告)号：US20160055898A1

公开(公告)日：2016-02-25

申请号：US14922973

申请日：2015-10-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuan Ruan ,  Mingyu Chen

IPC: G11C11/406 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/40607 ,  G06F12/02 ,  G06F13/1673 ,  G11C7/1063 ,  G11C7/1072

Abstract: A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delays a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem, reduces the memory access time.

Abstract translation: 第一级缓冲器芯片根据预先设定的映射关系对目标第二级缓冲器芯片进行门控，第一片选信号和第一高位地址信号，并转发存储器存取指令和从 内存控制器到目标二级缓冲芯片。 目标第二级缓冲器芯片根据第二芯片选择信号和通过延迟第二高阶地址信号获得的延迟地址信号来确定目标存储器模块，根据低阶地址信号确定目标存储器芯片，获取目标 根据存储器访问指令从目标存储器芯片获取数据，并将目标数据返回到存储器控制器。 系统存储器的级联方式更改为树形拓扑形式，避免了协议转换问题，减少了存储器访问时间。

公开(公告)号：US20150220448A1

公开(公告)日：2015-08-06

申请号：US14687607

申请日：2015-04-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyang Chen ,  Mingyu Chen ,  Zehan Cui ,  Yuan Ruan

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/35

CPC classification number: H03M7/6011 ,  G06F9/30138 ,  G06F9/35 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/385 ,  G06F17/30153 ,  G06F2212/6032 ,  G06F2212/657

Abstract: An address compression method, an address decompression method, a compressor, and a decompressor, which can improve an address compression ratio. The address compression method includes after a compressor receives multiple operation request messages that are sent by a first processor, determining, according to an address feature formed by address information carried in all operation request messages that have a same stream number, a compression algorithm corresponding to the operation request messages that have a same stream number; and then compressing, according to the determined compression algorithm, addresses carried in the operation request messages that have a same stream number. The present invention is applicable to the computer field.

Abstract translation: 地址压缩方法，地址解压缩方法，压缩器和解压缩器，可以提高地址压缩比。 地址压缩方法包括在压缩机接收到由第一处理器发送的多个操作请求消息之后，根据由具有相同流号的所有操作请求消息中携带的地址信息形成的地址特征，确定与 具有相同流号码的操作请求消息; 然后根据确定的压缩算法压缩具有相同流号的操作请求消息中承载的地址。 本发明可应用于计算机领域。

公开(公告)号：US10552337B2

公开(公告)日：2020-02-04

申请号：US15343693

申请日：2016-11-04

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/1009

Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

公开(公告)号：US10108553B2

公开(公告)日：2018-10-23

申请号：US15415344

申请日：2017-01-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yao Liu ,  Licheng Chen ,  Zehan Cui ,  Mingyu Chen

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.

公开(公告)号：US20170132148A1

公开(公告)日：2017-05-11

申请号：US15415344

申请日：2017-01-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yao Liu ,  Licheng Chen ,  Zehan Cui ,  Mingyu Chen

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/68 ,  G06F2212/681 ,  G06F2212/684

Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.

公开(公告)号：US20170091087A1

公开(公告)日：2017-03-30

申请号：US15373888

申请日：2016-12-09

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Zehan Cui ,  Mingyu Chen ,  Yongbing Huang

IPC: G06F12/02 ,  G06F12/1009 ,  G11C11/4096 ,  G06F3/06 ,  G11C11/406 ,  G11C11/4091

CPC classification number: G06F12/023 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/20 ,  G06F2212/657 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4091 ,  G11C11/4096

Abstract: A method for refreshing a dynamic random access memory DRAM and a computer system are provided. When an address of a refresh unit in a DRAM and refresh information of the refresh unit are acquired, the address of the refresh unit and the refresh information of the refresh unit are encapsulated as a DRAM access request, where the refresh unit is storage space on which one time of refresh is performed in the DRAM, and the refresh information of the refresh unit includes a refresh cycle of the refresh unit. Then, the address and the refresh information of the refresh unit are written into refresh data space using the DRAM access request, where the refresh data space is storage space that is preset in the DRAM and that is used for storing an address of at least one refresh unit and refresh information of the at least one refresh unit.

公开(公告)号：US20160085585A1

公开(公告)日：2016-03-24

申请号：US14954245

申请日：2015-11-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Licheng Chen ,  Lixin Zhang ,  Mingyu Chen

IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F9/4856 ,  G06F12/0215 ,  G06F12/0638 ,  G06F12/08 ,  G06F2212/1016 ,  G06F2212/205 ,  G06F2212/6024 ,  G06F2212/654

Abstract: A memory system, a method for processing a memory access request, and a computer system are provided. The memory system includes a first memory and a second memory that are of different types and separately configured to store operating data of a processor; a memory indexing table that stores a fetch address of a data unit block located in the first memory; a buffer scheduler configured to receive a memory access request of a memory controller, determine whether the data unit block corresponding to the fetch address is stored in the first memory or the second memory, and complete a fetch operation of the memory access request in the determined memory. A memory access request may be separately completed in different type of memory, which is transparent to an operating system, does not cause page fault, and can improve a memory access speed.

Abstract translation: 提供了存储器系统，用于处理存储器访问请求的方法和计算机系统。 存储器系统包括不同类型的第一存储器和第二存储器，并且分别配置为存储处理器的操作数据; 存储器索引表，其存储位于所述第一存储器中的数据单元块的获取地址; 配置为接收存储器控制器的存储器访问请求的缓冲器调度器，确定与取出地址相对应的数据单元块是否存储在第一存储器或第二存储器中，并且在确定的存储器访问请求中完成读取操作 记忆。 存储器访问请求可以在不同类型的存储器中单独完成，这对于操作系统是透明的，不会导致页面错误，并且可以提高存储器访问速度。

公开(公告)号：US20150302111A1

公开(公告)日：2015-10-22

申请号：US14754019

申请日：2015-06-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yinliang Yue ,  Jin Xiong ,  Lixin Zhang ,  Mingyu Chen

IPC: G06F17/30

CPC classification number: G06F16/84 ,  G06F16/10 ,  G06F16/13 ,  G06F16/188

Abstract: A method and an apparatus for constructing a file system in a key-value storage system. According to the method for constructing a file system in a key-value storage system disclosed by the present invention, a directory number corresponding to a directory path of a directory at each level is acquired first; then, according to the directory number and a file stored in the directory at each level, corresponding keywords Key of the directory and the file are constructed.

Abstract translation: 一种在键值存储系统中构建文件系统的方法和装置。 根据本发明公开的键值存储系统中的构造文件系统的方法，首先获取与各级的目录的目录路径对应的目录号码， 然后，根据目录号码和存储在每个级别的目录中的文件，构建目录和文件的对应关键字Key。