公开(公告)号：US20150006841A1

公开(公告)日：2015-01-01

申请号：US14335029

申请日：2014-07-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyu Chen ,  Yuan Ruan ,  Zehan Cui ,  Licheng Chen ,  Yongbing Huang ,  Mingyang Chen

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/4239

Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

Abstract translation: 公开了一种基于消息的存储器访问装置及其访问方法，基于消息的存储器访问装置包括：基于消息的命令总线，被配置为发送由CPU生成的基于消息的存储器访问指令，以指示存储器系统 执行相应的操作; 基于消息的存储器控​​制器，被配置为将CPU请求打包到消息分组中并将所述分组发送到存储模块，并且解析由所述存储模块返回的消息分组并将数据返回到所述CPU; 消息信道，被配置为发送请求消息分组和响应消息分组; 以及所述存储模块，包括缓冲器调度器，并且被配置为从所述基于消息的存储器控​​制器接收所述请求分组并处理相应的请求。

公开(公告)号：US10552337B2

公开(公告)日：2020-02-04

申请号：US15343693

申请日：2016-11-04

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/1009

Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

公开(公告)号：US10108553B2

公开(公告)日：2018-10-23

申请号：US15415344

申请日：2017-01-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yao Liu ,  Licheng Chen ,  Zehan Cui ,  Mingyu Chen

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.

公开(公告)号：US20170132148A1

公开(公告)日：2017-05-11

申请号：US15415344

申请日：2017-01-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yao Liu ,  Licheng Chen ,  Zehan Cui ,  Mingyu Chen

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/68 ,  G06F2212/681 ,  G06F2212/684

Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.

公开(公告)号：US20160085585A1

公开(公告)日：2016-03-24

申请号：US14954245

申请日：2015-11-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Licheng Chen ,  Lixin Zhang ,  Mingyu Chen

IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F9/4856 ,  G06F12/0215 ,  G06F12/0638 ,  G06F12/08 ,  G06F2212/1016 ,  G06F2212/205 ,  G06F2212/6024 ,  G06F2212/654

Abstract: A memory system, a method for processing a memory access request, and a computer system are provided. The memory system includes a first memory and a second memory that are of different types and separately configured to store operating data of a processor; a memory indexing table that stores a fetch address of a data unit block located in the first memory; a buffer scheduler configured to receive a memory access request of a memory controller, determine whether the data unit block corresponding to the fetch address is stored in the first memory or the second memory, and complete a fetch operation of the memory access request in the determined memory. A memory access request may be separately completed in different type of memory, which is transparent to an operating system, does not cause page fault, and can improve a memory access speed.

Abstract translation: 提供了存储器系统，用于处理存储器访问请求的方法和计算机系统。 存储器系统包括不同类型的第一存储器和第二存储器，并且分别配置为存储处理器的操作数据; 存储器索引表，其存储位于所述第一存储器中的数据单元块的获取地址; 配置为接收存储器控制器的存储器访问请求的缓冲器调度器，确定与取出地址相对应的数据单元块是否存储在第一存储器或第二存储器中，并且在确定的存储器访问请求中完成读取操作 记忆。 存储器访问请求可以在不同类型的存储器中单独完成，这对于操作系统是透明的，不会导致页面错误，并且可以提高存储器访问速度。

公开(公告)号：US20150301917A1

公开(公告)日：2015-10-22

申请号：US14754011

申请日：2015-06-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Mingyu Chen ,  Licheng Chen ,  Mingyang Chen

IPC: G06F11/30 ,  G06F13/16

CPC classification number: G06F11/3037 ,  G06F11/3027 ,  G06F11/3452 ,  G06F11/3466 ,  G06F12/10 ,  G06F12/12 ,  G06F13/1663 ,  G06F2201/815 ,  G06F2201/88

Abstract: A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.

Abstract translation: 内存监控方法和计算系统。 计算系统包括处理器，存储器和监视器。 监视器获取计算机系统的存储单元访问信息和处理信息。 存储器单元访问信息包括存储器的每个存储器单元的访问次数。 处理信息包括关于由当前运行进程访问的每个存储器单元的虚拟地址和物理地址之间的映射关系的信息。 在产生包括当前运行进程访问每个存储单元的频率的监视信息之后，根据存储器单元访问信息和处理信息，监视器将监视信息反馈给处理器。 因此，处理器可以根据监视信息执行存储器管理。

公开(公告)号：US10606746B2

公开(公告)日：2020-03-31

申请号：US16018602

申请日：2018-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Xu ,  Qun Yu ,  Licheng Chen

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

Abstract: An access request processing method and apparatus, and a computer system is disclosed. The computer system includes a processor and a non-volatile memory (NVM). When receiving a write request, the processor determines an object cache page according to the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.

公开(公告)号：US09898421B2

公开(公告)日：2018-02-20

申请号：US14751368

申请日：2015-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan ,  Licheng Chen

IPC: G06F12/02 ,  G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F12/1458 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C7/1003 ,  G11C7/1075

Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.

公开(公告)号：US09785551B2

公开(公告)日：2017-10-10

申请号：US14953320

申请日：2015-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Licheng Chen ,  Zehan Cui

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0284 ,  G06F13/1605 ,  G06F13/1673 ,  G06F2212/1044 ,  G06F2212/2532

Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

公开(公告)号：US20160371198A1

公开(公告)日：2016-12-22

申请号：US15257506

申请日：2016-09-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Licheng Chen ,  Mingyu Chen

IPC: G06F12/1027 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0842

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/6042 ,  G06F2212/651 ,  G06F2212/653 ,  G06F2212/657

Abstract: A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

Abstract translation: 一种用于高速缓存地址的映射处理方法和装置，其中该方法包括获取对应于由处理核心发送的访问地址的物理地址，其中物理地址包括物理页号（PPN）和页偏移量， 地址到缓存地址，其中缓存地址包括缓存集索引1，缓存标签，高速缓存集索引2和高速缓存块偏移顺序，其中高速缓存集索引1具有高位位，高速缓存 将低位位置索引2一起形成缓存集索引，缓存集索引1落在PPN的范围内。 巨大页面PPN的PPN的一些位被映射到Cache的设置索引，使得可以由操作系统对这些位进行着色。