公开(公告)号：US08914700B2

公开(公告)日：2014-12-16

申请号：US14025553

申请日：2013-09-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbo Cheng ,  Chenghong He ,  Kejia Lan

IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1048

Abstract: A method according to an embodiment of the present disclosure comprising: receiving a read instruction transmitted by a host device, the read instruction including a first address; reading first data together with a first CRC code and a first ECC which are associated with the first data from a memory based on the first address; and performing error detection on the first data based on the first CRC code, and performing error correction on the first data based on the first ECC if an error is detected. With the embodiments of the disclosure, the CRC code with better capability of error detection is adopted to perform error detection on the data. If any error is detected, error correction is performed using the ECC. Thus, it is possible to overcome the problem as to insufficient capability of error detection of the ECC in the prior art, thereby improving the system performance.

Abstract translation: 根据本公开的实施例的方法，包括：接收由主机设备发送的读指令，所述读指令包括第一地址; 基于第一地址从第一数据读取与第一数据相关联的第一CRC码和第一ECC的第一数据; 以及基于所述第一CRC码对所述第一数据执行错误检测，以及如果检测到错误，则基于所述第一ECC执行对所述第一数据的纠错。 利用本公开的实施例，采用具有更好的错误检测能力的CRC码来对数据执行错误检测。 如果检测到任何错误，则使用ECC执行纠错。 因此，可以克服现有技术中ECC的错误检测能力不足的问题，从而提高系统性能。

公开(公告)号：US20140164724A1

公开(公告)日：2014-06-12

申请号：US14132858

申请日：2013-12-18

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongbo Cheng ,  Chenghong He ,  Kejia Lan

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/1666 ,  G06F11/20

Abstract: A method and an apparatus for processing a system command during memory backup. The method includes: acquiring a write address corresponding to a write operation command; if data corresponding to the write address has been read from a raw memory area but is not written to a backup memory area, mapping the write operation command to the raw memory area, and writing data to the write address in the raw memory area according to the write operation command; and deducting a set value from the write address to obtain an initial address to subsequently read data from the raw memory area. According to the embodiments of the present invention, a problem of system command blocking is solved during a memory backup operation, so that a system command is processed in a timely manner.

Abstract translation: 一种在存储器备份期间处理系统命令的方法和装置。 该方法包括：获取与写入操作命令相对应的写入地址; 如果从原始存储器区域读取与写入地址相对应的数据，但是未写入到备份存储器区域，则将写入操作命令映射到原始存储器区域，并将数据写入原始存储区域中的写入地址，根据 写操作命令; 并从写入地址中扣除设定值以获得初始地址，以便随后从原始存储区读取数据。 根据本发明的实施例，在存储器备份操作期间解决了系统命令阻塞的问题，从而及时处理系统命令。

公开(公告)号：US20140013182A1

公开(公告)日：2014-01-09

申请号：US14025553

申请日：2013-09-12

Applicant: Huawei Technologies Co., LTD.

Inventor： Yongbo Cheng ,  Chenghong He ,  Kejia Lan

IPC: H03M13/29

CPC classification number: H03M13/2906 ,  G06F11/1048

Abstract: A method according to an embodiment of the present disclosure comprising: receiving a read instruction transmitted by a host device, the read instruction including a first address; reading first data together with a first CRC code and a first ECC which are associated with the first data from a memory based on the first address; and performing error detection on the first data based on the first CRC code, and performing error correction on the first data based on the first ECC if an error is detected. With the embodiments of the disclosure, the CRC code with better capability of error detection is adopted to perform error detection on the data. If any error is detected, error correction is performed using the ECC. Thus, it is possible to overcome the problem as to insufficient capability of error detection of the ECC in the prior art, thereby improving the system performance.

Abstract translation: 根据本公开的实施例的方法，包括：接收由主机设备发送的读指令，所述读指令包括第一地址; 基于第一地址从第一数据读取与第一数据相关联的第一CRC码和第一ECC的第一数据; 以及基于所述第一CRC码对所述第一数据执行错误检测，以及如果检测到错误，则基于所述第一ECC执行对所述第一数据的纠错。 利用本公开的实施例，采用具有更好的错误检测能力的CRC码来对数据执行错误检测。 如果检测到任何错误，则使用ECC执行纠错。 因此，可以克服现有技术中ECC的错误检测能力不足的问题，从而提高系统性能。

公开(公告)号：US20190057032A1

公开(公告)日：2019-02-21

申请号：US16165709

申请日：2018-10-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tao Li ,  Yongbo Cheng ,  Chenghong He

IPC: G06F12/0817 ,  G06F12/1009

CPC classification number: G06F12/0828 ,  G06F12/0824 ,  G06F12/1009 ,  G06F2212/621

Abstract: A cache coherence management method, a node controller, and a multiprocessor system that includes a first table, a second table, a node controller, and at least two nodes, where the node controller determines, in the first table according to address information of data, a first entry, where the first entry includes a first field and a second field. The first field records an occupation status of the data, the second field indicates a node that occupies the data exclusively when the first field includes an exclusive state, and the node controller determines a second entry in the second table according to the address information of the data and the second field when the first field includes a shared state, where the second entry includes a third field, and the third field indicates nodes that share the data.

公开(公告)号：US09880972B2

公开(公告)日：2018-01-30

申请号：US15150419

申请日：2016-05-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jiangen Liu ,  Chenghong He ,  Haibin Wang ,  Xinyu Hou

IPC: G06F9/30 ,  G06F15/80 ,  G06F15/173 ,  G06F15/167 ,  G06F13/42

CPC classification number: G06F15/80 ,  G06F13/4221 ,  G06F15/167 ,  G06F15/17337

Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

公开(公告)号：US09336179B2

公开(公告)日：2016-05-10

申请号：US13670718

申请日：2012-11-07

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jiangen Liu ,  Chenghong He ,  Haibin Wang ,  Xinyu Hou

IPC: G06F9/30 ,  G06F15/173 ,  G06F15/167

CPC classification number: G06F15/80 ,  G06F13/4221 ,  G06F15/167 ,  G06F15/17337

Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units CPUs and one node controller NC, where any two CPUs in each basic node are interconnected, each CPU in each basic node is connected to the NC in the basic node, the NC in each basic node has a routing function, any two NCs in the M basic nodes are interconnected, and a connection between the L composite nodes formed through a connection between NCs enable communication between any two NCs to require at most three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Abstract translation: 本发明提供一种计算机子系统和计算机系统。 计算机子系统包括L个复合节点，每个复合节点包括M个基本节点，每个基本节点包括N个中央处理单元CPU和一个节点控制器NC，其中每个基本节点中的任何两个CPU互连，每个基本节点中的每个CPU都连接 在基本节点中的NC中，每个基本节点中的NC具有路由功能，M个基本节点中的任何两个NC互连，并且通过NC之间的连接形成的L个复合节点之间的连接使得任何两个NC之间的通信 要求最多三跳。 根据本发明的实施例的计算机子系统和计算机系统可以减少互连芯片的种类和数量，并且简化系统的互连结构，从而提高系统的可靠性。

公开(公告)号：US10594607B2

公开(公告)日：2020-03-17

申请号：US15696900

申请日：2017-09-06

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Donghao Yu ,  Chenghong He ,  Ting Yang

IPC: H04L12/801 ,  H04L12/931 ,  H04L12/933 ,  H04L12/937

Abstract: The present invention discloses a switching apparatus, a switching apparatus group, a data transmission method, and a computer system, and pertains to the field of computer technologies. The switching apparatus includes: a selection circuit module, a SERDES module, and a scheduling module. The selection circuit module establishes at least (n−1) static links with each of n modes, and any two static links that are connected to the selection circuit module and that belong to different nodes are connected to each other. The SERDES module is disposed on a static link connected to the selection circuit module. The scheduling module establishes connections to the selection circuit module and each of the n nodes. The selection circuit module further establishes at least one dynamic link with each of the n nodes.

公开(公告)号：US20180107628A1

公开(公告)日：2018-04-19

申请号：US15845450

申请日：2017-12-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jiangen Liu ,  Chenghong He ,  Haibin Wang ,  Xinyu Hou

IPC: G06F15/80 ,  G06F15/173 ,  G06F15/167 ,  G06F13/42

CPC classification number: G06F15/80 ,  G06F13/4221 ,  G06F15/167 ,  G06F15/17337

Abstract: A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

公开(公告)号：US20180069794A1

公开(公告)日：2018-03-08

申请号：US15696900

申请日：2017-09-06

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Donghao YU ,  Chenghong He ,  Ting Yang

IPC: H04L12/801 ,  H04L12/933 ,  H04L12/937

Abstract: The present invention discloses a switching apparatus, a switching apparatus group, a data transmission method, and a computer system, and pertains to the field of computer technologies. The switching apparatus includes: a selection circuit module, a SERDES module, and a scheduling module. The selection circuit module establishes at least (n−1) static links with each of n modes, and any two static links that are connected to the selection circuit module and that belong to different nodes are connected to each other. The SERDES module is disposed on a static link connected to the selection circuit module. The scheduling module establishes connections to the selection circuit module and each of the n nodes. The selection circuit module further establishes at least one dynamic link with each of the n nodes.

公开(公告)号：US20170315916A1

公开(公告)日：2017-11-02

申请号：US15581599

申请日：2017-04-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbo Cheng ,  Kejia Lan ,  Chenghong He

IPC: G06F12/0817 ,  G06F12/0811

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0831 ,  G06F2212/621

Abstract: The present invention provide a directory management method including: receiving, by a first NC, a first data access request sent by a first processor on a local node; if the first NC determines that a first directory does not include a directory entry corresponding to a first access address and the first directory does not include an idle directory entry, clearing, by the first NC, directory content of a directory entry from the first directory; writing, by the first NC, directory content corresponding to the first data access request to the cleared directory entry; and if the first NC determines that a first snoop request is received, sending, by the first NC, a first snoop message to the processor on the local node.