公开(公告)号：US20210036702A1

公开(公告)日：2021-02-04

申请号：US16921571

申请日：2020-07-06

Applicant: Google LLC

Inventor： Houle Gan ,  Mikhail Popovich ,  Shuai Jiang ,  Gregory Sizikov ,  Chee Yee Chung

IPC: H03K17/687 ,  G06F1/26

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

公开(公告)号：US20240120847A1

公开(公告)日：2024-04-11

申请号：US17961264

申请日：2022-10-06

Applicant: Google LLC

Inventor： Shuai Jiang ,  Xin Li ,  Woon-Seong Kwon ,  Cheng Chung Yang ,  Qiong Wang ,  Nam Hoon Kim ,  Mikhail Popovich ,  Houle Gan ,  Chenhao Nan

IPC: H02M3/335 ,  H02M1/00

CPC classification number: H02M3/33576 ,  H02M1/0067 ,  H02M3/33571

Abstract: A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

公开(公告)号：US11552634B2

公开(公告)日：2023-01-10

申请号：US16921571

申请日：2020-07-06

Applicant: Google LLC

Inventor： Houle Gan ,  Mikhail Popovich ,  Shuai Jiang ,  Gregory Sizikov ,  Chee Yee Chung

IPC: H03K17/68 ,  H03K17/687 ,  G06F1/26 ,  H02M3/07

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

公开(公告)号：US11054891B2

公开(公告)日：2021-07-06

申请号：US16408088

申请日：2019-05-09

Applicant: Google LLC

Inventor： Mikhail Popovich ,  Gregory Sizikov

IPC: G06F1/32 ,  G06F1/06 ,  G06F1/10 ,  G06F1/3296 ,  G06F1/08

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If not failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

公开(公告)号：US10985652B1

公开(公告)日：2021-04-20

申请号：US16806521

申请日：2020-03-02

Applicant: Google LLC

Inventor： Shuai Jiang ,  Gregory Sizikov ,  Mikhail Popovich

IPC: G05F1/577 ,  H02M3/07 ,  G05F1/613 ,  G05F1/62 ,  G05F1/618

Abstract: This disclosure relates to power balancer circuits that enable multiple load zones of an IC to be powered in series while maintaining balanced voltage at each load zone. In one aspect, a circuit includes load zones that are powered in series. The circuit includes a power balancer for balancing a voltage across each load zone. The power balancer includes an equivalent DC transformer array that includes, for each load zone, an equivalent DC transformer connected in parallel with the load zone. The power balancer includes, for each load zone, a bus capacitor connected in parallel with the load zone. Each equivalent DC transformer is electrically connected to each other equivalent DC transformer providing an electrical path for each bus capacitor to discharge current to each other bus capacitor when a voltage across a bus capacitor is greater than a voltage across another bus capacitor.

公开(公告)号：US10742211B1

公开(公告)日：2020-08-11

申请号：US16527569

申请日：2019-07-31

Applicant: Google LLC

Inventor： Houle Gan ,  Mikhail Popovich ,  Shuai Jiang ,  Gregory Sizikov ,  Chee Yee Chung

IPC: H01L25/00 ,  H03K17/687 ,  G06F1/26 ,  H02M3/07

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.