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公开(公告)号：US20240415027A1
公开(公告)日：2024-12-12
申请号：US18736749
申请日：2024-06-07
Applicant: Google LLC
Inventor： Anthony Edward Megrant , Shiwen Liu , Brian Burkett
Abstract: Systems and methods for fabricating quantum hardware for use in a quantum computing system are provided. In one example, the system includes at least one metrology chamber operable to receive a workpiece. The workpiece includes a quantum structure associated with the quantum hardware. The metrology chamber includes at least one detector operable to characterize an atomic scale parameter associated with a surface of the quantum structure. The system includes at least one process chamber operable to receive the workpiece. The at least one process chamber is operable to perform a fabrication process on the quantum structure based at least in part on the atomic scale parameter. The system includes a transfer apparatus operable to transfer the workpiece between the at least one metrology chamber and the at least one process chamber without exposure to ambient.
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公开(公告)号：US11600763B2
公开(公告)日：2023-03-07
申请号：US16964053
申请日：2019-07-25
Applicant: Google LLC
Inventor： Brian James Burkett , Ofer Naaman , Anthony Edward Megrant , Theodore Charles White
Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.
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公开(公告)号：US20230043001A1
公开(公告)日：2023-02-09
申请号：US17971292
申请日：2022-10-21
Applicant: Google LLC
Inventor： Charles Neill , Anthony Edward Megrant
Abstract: Methods, systems and apparatus for implementing a tunable qubit coupler. In one aspect, a device includes: a first data qubit, a second data qubit, and a third qubit that is a tunable qubit coupler arranged to couple to the first data qubit and to couple to the second data qubit such that, during operation of the device, the tunable qubit coupler allows tunable coupling between the first data qubit and the second data qubit.
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公开(公告)号：US11508895B2
公开(公告)日：2022-11-22
申请号：US16333058
申请日：2016-09-14
Applicant: Google LLC
Inventor： Anthony Edward Megrant
Abstract: A device includes: a substrate including a superconductor quantum device, the superconductor quantum device including a superconductor material that exhibits superconducting properties at or below a corresponding critical temperature; a cap layer bonded to the substrate; and a sealed cavity between the cap layer and the substrate.
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公开(公告)号：US10727079B2
公开(公告)日：2020-07-28
申请号：US16332998
申请日：2016-09-13
Applicant: Google LLC
Inventor： Anthony Edward Megrant
IPC: H01L21/3205 , G03F7/09 , H01L39/24 , H01L39/00 , H01L27/18 , H01L29/43 , H01L21/28 , H01L21/768 , G03F7/11 , C09D133/12 , G03F7/16 , G03F7/20 , G03F7/32 , H01L39/12
Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20190393401A1
公开(公告)日：2019-12-26
申请号：US16557116
申请日：2019-08-30
Applicant: Google LLC
Inventor： Anthony Edward Megrant
Abstract: A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.
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公开(公告)号：US20190227439A1
公开(公告)日：2019-07-25
申请号：US16332998
申请日：2016-09-13
Applicant: Google LLC
Inventor： Anthony Edward Megrant
Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.
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公开(公告)号：US20240023461A1
公开(公告)日：2024-01-18
申请号：US18198192
申请日：2023-05-16
Applicant: Google LLC
Inventor： Anthony Edward Megrant
CPC classification number: H10N60/0912 , G06N10/00 , H10N60/01
Abstract: A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material on a principal surface of a substrate, depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.
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公开(公告)号：US11690301B2
公开(公告)日：2023-06-27
申请号：US17405448
申请日：2021-08-18
Applicant: Google LLC
Inventor： Anthony Edward Megrant
CPC classification number: H10N60/83 , G06N10/00 , H10N60/01 , H10N69/00 , H01L21/76891 , H10N60/0912 , H10N60/10 , H10N60/855
Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.
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公开(公告)号：US11593696B2
公开(公告)日：2023-02-28
申请号：US16870372
申请日：2020-05-08
Applicant: Google LLC
Inventor： Charles Neill , Anthony Edward Megrant , Yu Chen
IPC: G06N10/00
Abstract: Methods, systems and apparatus for implementing a target two-qubit quantum logic gate on a first qubit and second qubit using a tunable qubit coupler. In one aspect, a method includes generating a control signal for the target two-qubit quantum logic gate according to a control model, wherein the control model comprises a controlled-Z operator and a swap operator that are non-orthogonal; and applying the control signal to the first qubit, second qubit and tunable qubit coupler.
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