公开(公告)号：US09419101B1

公开(公告)日：2016-08-16

申请号：US14932394

申请日：2015-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Zhao Lun ,  Tao Han ,  Hsien-Ching Lo ,  Basab Banerjee ,  Wen Zhi Gao ,  Byoung-Gi Min

IPC: H01L21/8232 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.

Abstract translation: 提供了形成间隔物的方法和所得的鳍状场效应晶体管。 实施例包括在衬底上形成硅（Si）鳍; 在Si鳍上形成多晶硅栅极; 以及在所述多晶硅栅极的顶表面和侧表面上形成间隔物，并且在所述Si鳍的暴露的上表面和外表面上，所述间隔物包括：具有第一介电常数的第一层和第二层，以及形成在所述第一 和第二层并具有第二介电常数，其中第二介电常数低于第一介电常数。

公开(公告)号：US20150380515A1

公开(公告)日：2015-12-31

申请号：US14319462

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Xusheng Wu ,  Hong Yu ,  Zhao Lun

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

Abstract translation: 提供了用于形成外延（epi）源极/漏极（S / D）和/或具有外延S / D的半导体器件的方法。 在本发明的实施例中，epi S / D的第一部分形成在鳍状衬底中的翅片上的S / D区域中。 在形成第一部分之后，但在形成S / D之前，在S / D区域中形成二次间隔物。 然后，在S / D区域中形成S / D的剩余部分。 结果，S / D通过辅助间隔件与栅极堆叠分离。

公开(公告)号：US20200287019A1

公开(公告)日：2020-09-10

申请号：US16296769

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Hong Yu ,  Man Gu ,  Jianwei Peng ,  Michael Aquilino

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US10446483B2

公开(公告)日：2019-10-15

申请号：US15872589

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Jianwei Peng ,  Xusheng Wu ,  Yi Qi ,  Jeffrey Chee

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

公开(公告)号：US10410929B2

公开(公告)日：2019-09-10

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jianwei Peng ,  Yi Qi ,  Hsien-Ching Lo ,  Jerome Ciavatti ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L21/20

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

公开(公告)号：US20190181243A1

公开(公告)日：2019-06-13

申请号：US16276045

申请日：2019-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/161

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US10276689B2

公开(公告)日：2019-04-30

申请号：US15615925

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Ruilong Xie ,  Xunyuan Zhang ,  Hui Zang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

公开(公告)号：US20190103319A1

公开(公告)日：2019-04-04

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/088

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US10249538B1

公开(公告)日：2019-04-02

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/311

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US20180323269A1

公开(公告)日：2018-11-08

申请号：US15585865

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material