公开(公告)号：US20230083225A1

公开(公告)日：2023-03-16

申请号：US17943528

申请日：2022-09-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jong-Heon YANG ,  Seung Youl KANG ,  Yong Hae KIM ,  Hee-ok KIM ,  Jeho NA ,  Jaehyun MOON ,  Chan Woo PARK ,  Himchan OH ,  Seong-Mok CHO ,  Sung Haeng CHO ,  Ji Hun CHOI ,  Jae-Eun PI ,  Chi-Sun HWANG

IPC: H01L27/32 ,  G09G3/3266 ,  G09G3/3225

Abstract: Provided are a semiconductor device, a display panel, and a display device including the same. The semiconductor device includes a lower electrode on one side of a substrate, a spacer on another side of the substrate, a middle electrode on the spacer, a lower channel layer on portions of a sidewall of the spacer, the middle electrode, and the lower electrode, a lower gate insulating layer on the lower channel layer, a common gate electrode on the gate insulating layer, an upper gate insulating layer on the common gate electrode, an upper electrode on the spacer and the upper gate insulating layer of the middle electrode, an upper channel layer connected to the upper electrode and disposed on a sidewall of the upper gate insulating layer, and a contact electrode connected to a portion of the upper channel layer and passing through the lower gate insulating layer and the upper gate insulating layer outside the common gate electrode so as to be connected to the lower electrode.

公开(公告)号：US20250120159A1

公开(公告)日：2025-04-10

申请号：US18887701

申请日：2024-09-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Haeng CHO ,  Chihun SUNG ,  Sooji NAM

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Provided is a thin film transistor including a substrate, a channel layer on the substrate, a first source/drain electrode and a second source/drain electrode spaced apart on the substrate and on the channel layer in a first direction parallel to the substrate, a gate insulation layer on the substrate, the channel layer, the first source/drain electrode, and the second source/drain electrode, and a gate electrode on the gate insulation layer between the first and second source/drain electrodes, wherein the uppermost level of the gate electrode is substantially the same as the uppermost level of the gate insulation layer.

公开(公告)号：US20230097393A1

公开(公告)日：2023-03-30

申请号：US17520853

申请日：2021-11-08

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Haeng CHO ,  Byung-Do YANG ,  Sooji NAM ,  Jaehyun MOON ,  Jae-Eun PI ,  Jae-Min KIM

IPC: H01L27/092 ,  H01L29/24 ,  H03K19/0185 ,  H03K19/0948 ,  H01L27/02

Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

公开(公告)号：US20190221761A1

公开(公告)日：2019-07-18

申请号：US16204869

申请日：2018-11-29

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chi-Sun HWANG ,  Seung Youl KANG ,  Byoung-Hwa KWON ,  Gi Heon KIM ,  Seong Hyun KIM ,  Jaehyun MOON ,  Young Sam PARK ,  Seongdeok AHN ,  JEONG IK LEE ,  Sung Haeng CHO

IPC: H01L51/00 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56 ,  B32B7/12 ,  B32B27/08

Abstract: Provided is a stretchable display including an elastic body, a light emitting unit on the elastic body, and a wiring unit on the elastic body, wherein the light emitting unit includes a first substrate unit on the elastic body, a buffer layer on the first substrate unit, and a light emitting element on the buffer layer, the wiring unit includes a second substrate unit on the elastic body, a driving element configured to control the light emitting element, a wiring configured to electrically connect the driving element and the light emitting element, and an insulation layer configured to cover the driving element and the wiring, the light emitting unit and the wiring unit have respective corrugation structures, a thickness of the light emitting unit is larger than that of the wiring unit, a modulus of elasticity of the buffer layer is larger than that of the insulation layer, and a modulus of elasticity of the elastic body is smaller than that of the insulation layer.

公开(公告)号：US20190213380A1

公开(公告)日：2019-07-11

申请号：US16219373

申请日：2018-12-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chul Woong JOO ,  Jonghee LEE ,  Jae-Eun PI ,  Byoung-Hwa KWON ,  Hyunsu CHO ,  Seung Youl KANG ,  Seongdeok AHN ,  Jeong Ik LEE ,  Nam Sung CHO ,  Sung Haeng CHO ,  Woojin SUNG ,  Jongchan LEE

IPC: G06K9/00

CPC classification number: G06K9/0004 ,  H01L51/5215 ,  H01L51/5234 ,  H01L51/5237

Abstract: Provided is an optical fingerprint recognition sensor. The optical fingerprint recognition sensor includes a transparent light emitting unit configured to emit light to a fingerprint, a light receiving unit disposed below the light emitting unit to vertically overlap the light emitting unit and configured to receive light reflected by the fingerprint, and a control unit disposed below the light emitting unit to vertically overlap the light emitting unit and configured to control the light emitting unit and the light receiving unit. The light emitting unit includes an organic layer.