公开(公告)号：US10608102B2

公开(公告)日：2020-03-31

申请号：US16137235

申请日：2018-09-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hokyun Ahn ,  Min Jeong Shin ,  Jeong Jin Kim ,  Hae Cheon Kim ,  Jae Won Do ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hyung Seok Lee ,  Jong-Won Lim ,  Sungjae Chang ,  Hyunwook Jung ,  Kyu Jun Cho ,  Dong Min Kang ,  Dong-Young Kim ,  Seong-Il Kim ,  Sang-Heung Lee ,  Jongmin Lee ,  Hong Gu Ji

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/417 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423

Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.

公开(公告)号：US10256811B2

公开(公告)日：2019-04-09

申请号：US15654792

申请日：2017-07-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojin Chang ,  Jong-Won Lim ,  Dong Min Kang ,  Dong-Young Kim ,  Seong-il Kim ,  Hae Cheon Kim ,  Jae Won Do ,  Byoung-Gue Min ,  Min Jeong Shin ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Sang-Heung Lee ,  Jongmin Lee ,  Sungjae Chang ,  Yoo Jin Jang ,  Hyunwook Jung ,  Kyu Jun Cho ,  Hong Gu Ji

IPC: H03K17/687 ,  H03K17/693 ,  G11C5/14 ,  H03K19/0175 ,  H03K3/353 ,  H03K17/0812 ,  H03K17/10 ,  H03K17/12 ,  H03K17/14 ,  H03K17/16 ,  H03K17/28

Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.

公开(公告)号：US08941231B2

公开(公告)日：2015-01-27

申请号：US13938324

申请日：2013-07-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young Rak Park ,  Sang Choon Ko ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Sung-Bum Bae ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L23/12 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L29/66477 ,  H01L23/5225 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

Abstract translation: 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。

公开(公告)号：US08901608B2

公开(公告)日：2014-12-02

申请号：US13908076

申请日：2013-06-03

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jong-Won Lim ,  Hokyun Ahn ,  Woojin Chang ,  Dong Min Kang ,  Seong-Il Kim ,  Sang-Heung Lee ,  Hyung Sup Yoon ,  Chull Won Ju ,  Hae Cheon Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L33/00 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/778 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66431

Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.

Abstract translation: 高电子迁移率晶体管包括设置在源极和漏极之间的衬底上的T型栅电极和设置在衬底和T型栅电极之间的绝缘层。 绝缘层包括第一绝缘层，第二绝缘层和第三绝缘层。 第三绝缘层设置在基板和T型栅电极的头部之间，使得第三绝缘层的一部分与T型栅极的脚部接触。 第二绝缘层设置在基板与T型栅电极的头部之间以与第三绝缘层接触。 所述第一绝缘层和所述第三绝缘层的另一部分依次层叠在所述基板与所述T型栅电极的头部之间，以与所述第二绝缘层接触。