公开(公告)号：US20170201247A1

公开(公告)日：2017-07-13

申请号：US15217271

申请日：2016-07-22

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Woojin CHANG ,  Sang Choon KO ,  Jae Kyoung MUN ,  Young Rak PARK

IPC: H03K17/081 ,  H03K17/74

CPC classification number: H03K17/08104 ,  H03K17/0822 ,  H03K17/74

Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.

公开(公告)号：US20150194363A1

公开(公告)日：2015-07-09

申请号：US14324724

申请日：2014-07-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chi Hoon JUN ,  Sang Choon KO ,  Seok-Hwan MOON ,  Woojin CHANG ,  Sung-Bum BAE ,  Young Rak PARK ,  Je Ho NA ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC: H01L23/367 ,  H01L21/3205 ,  H01L23/467 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/473

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：设置在衬底上的有源区; 入口通道形成为隐藏在所述基板的一侧中的单个腔; 出口通道形成为埋在基板的另一侧中的单个腔; 微通道阵列，其包括多个微通道，其中所述多个微通道形成为埋在所述衬底中的多个空腔，并且所述微通道阵列的一端连接到所述入口通道的一侧，而另一端 的微通道阵列连接到出口通道的一侧; 以及将微通道彼此分离的微型散热器阵列。

公开(公告)号：US20140149099A1

公开(公告)日：2014-05-29

申请号：US13911189

申请日：2013-06-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojin CHANG

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G01R27/28 ,  H01L23/66 ,  H01L2924/0002 ,  H04B17/0085 ,  H01L2924/00

Abstract: Provided is a method of configuring a large signal model of an active device. The method may include configuring a large signal model of a first active device, preparing a first measured value on a first characteristic of a second active device, the second active device being larger than the first active device, processing the large signal model of the first active device using a circuit simulator to configure a large signal model of the second active device, simulating the large signal model of the second active device to obtain a calculated value on the first characteristic, comparing the measured and calculated values on the first characteristic to each other, and establishing the large signal model of the second active device, if a difference between the measured and calculated values on the first characteristic may be smaller than a predetermined error margin. Further, if the difference between the measured and calculated values on the first characteristic may be greater than the predetermined error margin, the large signal model of the second active device may be configured by modifying parameters of passive devices.

Abstract translation: 提供了一种配置有源器件的大信号模型的方法。 该方法可以包括配置第一有源器件的大信号模型，在第二有源器件的第一特性上准备第一测量值，第二有源器件大于第一有源器件，处理第一有源器件的大信号模型 主动装置，使用电路模拟器来配置第二有源装置的大信号模型，模拟第二有源装置的大信号模型以获得关于第一特性的计算值，将第一特性上的测量值和计算值与每个 如果第一特性上的测量值和计算值之间的差可能小于预定的误差容限，则建立第二有源器件的大信号模型。 此外，如果第一特性上的测量值和计算值之间的差可以大于预定误差容限，则可以通过修改无源器件的参数来配置第二有源器件的大信号模型。

公开(公告)号：US20130244379A1

公开(公告)日：2013-09-19

申请号：US13875795

申请日：2013-05-02

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Woojin CHANG

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L23/49805 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/24147 ,  H01L2224/24195 ,  H01L2224/73259 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.

Abstract translation: 提供一种半导体封装及其制造方法。 半导体封装包括：包括多个片的封装体; 半导体芯片安装在封装体内; 以及设置在所述封装主体的第一侧上的外部连接端子，其中所述片材沿与所述第一侧平行的方向堆叠。