公开(公告)号：US09184063B2

公开(公告)日：2015-11-10

申请号：US13939801

申请日：2013-07-11

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong Suk Yang ,  In-Kyu You ,  Jae Bon Koo ,  Yong-Young Noh

IPC: H01L21/48 ,  H05K1/09 ,  H05K1/03 ,  H05K1/02 ,  H01L23/498 ,  H05K3/40 ,  H05K3/10 ,  H05K3/12

CPC classification number: H01L21/4814 ,  H01L21/4867 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0277 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/105 ,  H05K3/125 ,  H05K3/4069 ,  H05K2203/1105 ,  H05K2203/125 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are a multi-layer interconnection structure and a manufacturing method thereof. The multi-layer interconnection structure includes a substrate; a first wiring on the substrate; an interlayer insulation layer on the first wiring; a second wiring on the interlayer insulation layer; and a via contact including at least one conductive filament penetrating through the interlayer insulation layer between the second wiring and the first wiring to be electrically connected to the first wiring and the second wiring.

Abstract translation: 提供一种多层互连结构及其制造方法。 多层互连结构包括基板; 在基板上的第一布线; 第一布线上的层间绝缘层; 层间绝缘层上的第二布线; 以及通孔接触，其包括穿过所述第二布线和所述第一布线之间的所述层间绝缘层的至少一个导电丝，以电连接到所述第一布线和所述第二布线。

公开(公告)号：US20140076610A1

公开(公告)日：2014-03-20

申请号：US13934635

申请日：2013-07-03

Applicant: Electronics and Telecommunications Research Institute

Inventor： Yong Suk YANG ,  In-Kyu You ,  Minseok Kim ,  Soon-Won Jung ,  Bock Soon Na ,  Sang Chul Lim

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/02 ,  H01L51/0022 ,  H01L51/003 ,  H01L51/102 ,  H01L51/441 ,  H01L51/5203 ,  H05K1/0393 ,  H05K3/0058 ,  H05K3/207 ,  H05K2201/0376

Abstract: Disclosed are a method for manufacturing a planarizing printed electronic device and a planarizing printed electronic device manufactured by using the same by simply implementing a large-area embedded printed electronic device by coupling a printing process such as inkjet printing and gravure printing and a transferring process using a laminating device and particularly, solving defects due to large surface roughness and a thickness of a printed layer included in the printed electronic device, when manufacturing an embedded printed electronic device where a printed layer is embedded in a substrate.

Abstract translation: 公开了一种制造平面印刷电子器件的方法和通过使用它们简单地实现大面积嵌入式印刷电子器件而制造的平面化印刷电子器件，其通过联接诸如喷墨印刷和凹版印刷的印刷工艺和使用 层压装置，特别是在制造嵌入印刷电子器件时，其中印刷层嵌入基板中，特别是解决了印刷电子器件中包括的印刷层的大的表面粗糙度和厚度的缺陷。

公开(公告)号：US08653631B2

公开(公告)日：2014-02-18

申请号：US13775280

申请日：2013-02-25

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jae Bon Koo ,  Jong-Hyun Ahn ,  Seung Youl Kang ,  Hasan Musarrat ,  In-Kyu You ,  Kyoung Ik Cho

IPC: H01L29/06

CPC classification number: H01L27/1266 ,  H01L27/1214 ,  H01L27/1218 ,  H01L29/78603

Abstract: Provided are a transferred thin film transistor and a method of manufacturing the same. The method includes: forming a source region and a drain region that extend in a first direction in a first substrate and a channel region between the source region and the drain region; forming trenches that extend in a second direction in the first substrate to define an active layer between the trenches, the second direction intersecting the first direction; separating the active layer between the trenches from the first substrate by performing an anisotropic etching process on the first substrate inside the trenches; attaching the active layer on a second substrate; and forming a gate electrode in the first direction on the channel region of the active layer.

Abstract translation: 提供了一种转移的薄膜晶体管及其制造方法。 该方法包括：形成在第一衬底中沿第一方向延伸的源极区域和漏极区域以及源极区域和漏极区域之间的沟道区域; 形成在所述第一衬底中沿第二方向延伸的沟槽，以在所述沟槽之间限定有源层，所述第二方向与所述第一方向相交; 通过在所述沟槽内的所述第一衬底上进行各向异性蚀刻工艺，从所述第一衬底分离所述沟槽之间的有源层; 将活性层附着在第二基底上; 以及在有源层的沟道区上沿第一方向形成栅电极。