公开(公告)号：US07725647B2

公开(公告)日：2010-05-25

申请号：US11679732

申请日：2007-02-27

Applicant: Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

Inventor： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0607

Abstract: A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

Abstract translation: 存储器装置包括被配置为根据预定义的协议以数据分组的形式发送数据的接口。 存储器装置包括至少两个存储体。 每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其配置成便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 该存储器装置包括被配置为对数据包进行编码和/或解码的至少两个数据包处理装置。 至少两个数据分组处理设备被分配给不同的存储体存取设备。

公开(公告)号：US07576619B2

公开(公告)日：2009-08-18

申请号：US10520805

申请日：2003-07-11

Applicant: Daniel Kehrer ,  Herbert Knapp

Inventor： Daniel Kehrer ,  Herbert Knapp

IPC: H03B1/04 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03F3/45183 ,  H01L2924/0002 ,  H03F2203/45562 ,  H03F2203/45638 ,  H03H7/0115 ,  H01L2924/00

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes an output circuit having at least one first output connection which can provide a data signal, at least one first data output connection; and at least one first inductance connected between the at least one first output connection and the at least one data output connection.

Abstract translation: 公开了一种集成电路装置。 在一个实施例中，集成电路装置包括具有至少一个第一输出连接的输出电路，其可以提供数据信号，至少一个第一数据输出连接; 以及连接在所述至少一个第一输出连接和所述至少一个数据输出连接之间的至少一个第一电感。

公开(公告)号：US20070201296A1

公开(公告)日：2007-08-30

申请号：US11679732

申请日：2007-02-27

Applicant: Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

Inventor： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

IPC: G11C8/00

CPC classification number: G06F12/0607

Abstract: A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

Abstract translation: 存储器装置包括被配置为根据预定义的协议以数据分组的形式发送数据的接口。 存储器装置包括至少两个存储体。 每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其配置成便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 该存储器装置包括被配置为对数据包进行编码和/或解码的至少两个数据包处理装置。 至少两个数据分组处理设备被分配给不同的存储体存取设备。

公开(公告)号：US09203451B2

公开(公告)日：2015-12-01

申请号：US13325935

申请日：2011-12-14

Applicant: Daniel Kehrer ,  Kai Jung

Inventor： Daniel Kehrer ,  Kai Jung

IPC: H04B1/00 ,  H04B1/10 ,  H04B1/18 ,  H03H7/01

CPC classification number: H04B1/1036 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H04B1/109 ,  H04B1/18

Abstract: In accordance with an embodiment, a radio-frequency (RF) front-end for a radio configured to receive an RF signal at a first frequency includes an antenna port configured to be coupled to an antenna, and a notch filter having an input coupled to the antenna port. The notch filter is configured to reject one or more frequencies, such that the first frequency is a harmonic or intermodulation distortion product of the one or more frequencies. The RF front-end also includes a piezoelectric filter having an input coupled to an output of the notch filter and an output configured to be coupled to an RF amplifier. The piezoelectric filter has a pass band comprising the first frequency.

Abstract translation: 根据实施例，被配置为以第一频率接收RF信号的无线电的射频（RF）前端包括被配置为耦合到天线的天线端口和陷波滤波器，其具有耦合到 天线端口。 陷波滤波器被配置为拒绝一个或多个频率，使得第一频率是一个或多个频率的谐波或互调失真积。 RF前端还包括压电滤波器，其具有耦合到陷波滤波器的输出的输入和被配置为耦合到RF放大器的输出。 压电滤波器具有包括第一频率的通带。

公开(公告)号：US08749056B2

公开(公告)日：2014-06-10

申请号：US13116285

申请日：2011-05-26

Applicant: Daniel Kehrer ,  Stefan Martens ,  Tze Yang Hin ,  Helmut Wietschorke ,  Horst Theuss ,  Beng Keh See ,  Ulrich Krumbein

Inventor： Daniel Kehrer ,  Stefan Martens ,  Tze Yang Hin ,  Helmut Wietschorke ,  Horst Theuss ,  Beng Keh See ,  Ulrich Krumbein

IPC: H01L23/34

CPC classification number: H01L23/495 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/16 ,  H01L2223/6611 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Abstract translation: 公开了一种用于制造模块的模块和方法。 模块的实施例包括第一半导体器件，布置在第一半导体器件上的框架，包括空腔的框架和布置在框架上的第二半导体器件，其中第二半导体器件密封空腔。

公开(公告)号：US20140015614A1

公开(公告)日：2014-01-16

申请号：US13545732

申请日：2012-07-10

Applicant: Paulo Oliveira ,  Daniel Kehrer

Inventor： Paulo Oliveira ,  Daniel Kehrer

IPC: H03F3/14

CPC classification number: H03F1/26 ,  H03F1/223 ,  H03F1/347 ,  H03F3/191 ,  H03F3/195 ,  H03F2200/294

Abstract: In accordance with an embodiment, a low noise amplifier (LNA) includes a transistor, and a transformer having a first winding coupled between a LNA input terminal and a control node of the transistor, and a second winding magnetically coupled to the first winding coupled between a reference node of the transistor and a LNA reference terminal. An output of the LNA is coupled to an output node of the transistor.

Abstract translation: 根据实施例，低噪声放大器（LNA）包括晶体管和具有耦合在LNA输入端子和晶体管的控制节点之间的第一绕组的变压器，以及磁耦合到耦合在晶体管的第一绕组之间的第一绕组的第二绕组 晶体管的参考节点和LNA参考端子。 LNA的输出耦合到晶体管的输出节点。

公开(公告)号：US08351496B2

公开(公告)日：2013-01-08

申请号：US11760450

申请日：2007-06-08

Applicant: Daniel Kehrer ,  Franz Weiss

Inventor： Daniel Kehrer ,  Franz Weiss

IPC: H03H7/30

CPC classification number: H03H17/0219 ,  H03H15/00 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0245

Abstract: An integrated circuit having a filter apparatus for filtering a first symbol sequence is disclosed. The first symbol sequence has a predetermined symbol duration. The apparatus includes at least one delay device which is clocked in accordance with a clock, and configured to delay the first symbol sequence by a delay time. A relationship between the delay time of the delay device and a clock duration of the clocked delay device has a predetermined value which is not equal to the one.

Abstract translation: 公开了一种具有用于滤波第一符号序列的滤波器装置的集成电路。 第一符号序列具有预定的符号持续时间。 该装置包括至少一个根据时钟计时并延迟第一符号序列延迟时间的延迟装置。 延迟装置的延迟时间与时钟延迟装置的时钟持续时间之间的关系具有不等于预定值的预定值。

公开(公告)号：US20090225919A1

公开(公告)日：2009-09-10

申请号：US12042599

申请日：2008-03-05

Applicant: Franz Weiss ,  Daniel Kehrer

Inventor： Franz Weiss ,  Daniel Kehrer

IPC: H04L7/00 ,  H04L25/00

CPC classification number: H04J3/047 ,  H04J3/0685

Abstract: Embodiments of the invention relate to integrated circuits comprising inputs for receiving an input signal and a plurality of clock signals having a predetermined phase relationship. The integrated circuit may include a plurality of track-and-hold devices and a plurality of slicer devices. Signal outputs of two track-and-hold devices may be coupled to signal inputs of one slicer device, one of the two track-and-hold devices and the slicer device being coupled to a first input configured to receive a first clock signal and the other track-and-hold device being coupled to a second input being configured to receive a second clock signal.

Abstract translation: 本发明的实施例涉及包括用于接收输入信号和具有预定相位关系的多个时钟信号的输入的集成电路。 集成电路可以包括多个跟踪和保持设备以及多个限幅器设备。 两个跟踪和保持设备的信号输出可以耦合到一个限幅器设备的信号输入，两个跟踪和保持设备中的一个和限幅器设备被耦合到被配置为接收第一时钟信号的第一输入端，并且 耦合到第二输入的其它跟踪和保持设备被配置为接收第二时钟信号。