-
公开(公告)号：US10476444B1
公开(公告)日：2019-11-12
申请号：US16142498
申请日：2018-09-26
Inventor： Tejasvi Das , Xin Zhao , Ku He , Nishant Jain , Lei Zhu , Xiaofan Fei
Abstract: A system may include a plurality of playback paths comprising an open-loop playback path configured to drive an output load and a closed-loop playback path. The closed-loop playback path may include an outer feedback loop comprising one or more integrators, a quantizer, and an output driver for driving the output load, the outer feedback loop having an outer loop feedback gain and an inner feedback loop comprising the one or more integrators and the quantizer and excluding the output driver, wherein the inner feedback loop has a variable inner loop feedback gain which is adjustable to match the outer loop feedback gain.
-
公开(公告)号：US20190149096A1
公开(公告)日：2019-05-16
申请号：US16249619
申请日：2019-01-16
Inventor： Lei Zhu , Xin Zhao , John L. Melanson
Abstract: Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
-
公开(公告)号：US10263584B1
公开(公告)日：2019-04-16
申请号：US16133045
申请日：2018-09-17
Inventor： Tejasvi Das , Alan Mark Morton , Xin Zhao , Lei Zhu , Xiaofan Fei , Johann G. Gaboriau , John L. Melanson , Amar Vellanki
IPC: H03G3/30 , H03F3/187 , H04R3/00 , H03K17/687
Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
-
公开(公告)号：US10224877B2
公开(公告)日：2019-03-05
申请号：US15581057
申请日：2017-04-28
Inventor： Lei Zhu , Xin Zhao , John L. Melanson
IPC: H03F3/38 , H03F1/02 , H03F1/56 , H03F3/183 , H03F3/217 , H03G3/30 , H03F1/30 , H03F1/32 , H03F3/187 , H03M1/66
Abstract: Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
-
公开(公告)号：US10164576B2
公开(公告)日：2018-12-25
申请号：US15582233
申请日：2017-04-28
Inventor： Graeme Gordon MacKay , Lei Zhu , Ku He , Vamsikrishna Parupalli
Abstract: In accordance with embodiments of the present disclosure, a method for power supply rejection for an amplifier may include generating a correction signal by multiplying a quantity indicative of a power supply voltage of the amplifier by a transfer function defining a response from the power supply voltage of the amplifier to an output signal of the amplifier and subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.
-
Patent Agency Ranking
公开(公告)号：US10008992B1
公开(公告)日：2018-06-26
申请号：US15487555
申请日：2017-04-14
Inventor： Lei Zhu , Xin Zhao , Alan Mark Morton , Tejasvi Das , Ku He , Xiaofan Fei
CPC classification number: H03F3/2178 , H03F1/0277 , H03F3/30 , H03F2200/03 , H03F2200/411 , H03F2200/432
Abstract: An amplifier may include a final output stage switchable among a plurality of modes comprising a mode which is enabled by coupling an output driver to an output of the final output stage and a preconditioning circuit coupled to the output of the final output stage. The preconditioning circuit may be configured to precondition at least one of a voltage and a current of the output of the final output stage prior to coupling the output driver to the output of the final output stage to limit audio artifacts caused by switching the final output stage to the mode or may be configured to perform a switching sequence to switch between a first mode and a second mode of the plurality of modes, such that at all points of the switching sequence, output terminals of the output of the final output stage have a known impedance.
-
公开(公告)号：US11798978B2
公开(公告)日：2023-10-24
申请号：US17019621
申请日：2020-09-14
Inventor： John L. Melanson , Lei Zhu , Wai-Shun Shum , Xiaofan Fei , Johann G. Gaboriau
IPC: H01L23/52 , H01L49/02 , H03F1/02 , H01L23/522
CPC classification number: H01L28/10 , H01L23/5227 , H03F1/0272
Abstract: A single integrated circuit may include a signal path configured to generate an output signal from an input signal, wherein the signal path includes an amplifier configured to drive the output signal, a direct-current-to-direct-current (DC-DC) power converter having a power inductor integrated in the single integrated circuit and configured to generate a supply voltage to the amplifier from a source voltage to the DC-DC power converter, and control circuitry for controlling operation of converter switches of the DC-DC power converter in order that the supply voltage tracks at least one among the input signal and the output signal.
-
公开(公告)号：US10651801B2
公开(公告)日：2020-05-12
申请号：US16249619
申请日：2019-01-16
Inventor： Lei Zhu , Xin Zhao , John L. Melanson
IPC: H03F3/38 , H03F1/02 , H03F1/56 , H03F3/183 , H03F3/217 , H03G3/30 , H03F1/30 , H03F1/32 , H03F3/187 , H03M1/08 , H03M1/66
Abstract: Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
-
公开(公告)号：US10236827B2
公开(公告)日：2019-03-19
申请号：US15622722
申请日：2017-06-14
Inventor： Lei Zhu , Ku He , Xin Zhao , Miao Song , Saurabh Singh , Vinod Jayakumar
Abstract: A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.
-
20.发明申请公开(公告)号：US20210175894A1
公开(公告)日：2021-06-10
申请号：US16942062
申请日：2020-07-29
Inventor： John L. MELANSON , Johann G. GABORIAU , Lei Zhu , Wai-Shun Shum , Xiaofan Fei , Leyi Yin
Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.
-
-
-
-
-
-
-
-
-
Search Results
31
records
(took 0.018 seconds)
