Gain and mismatch calibration for a phase detector used in an inductive sensor

    公开(公告)号:US12085525B2

    公开(公告)日:2024-09-10

    申请号:US18470066

    申请日:2023-09-19

    IPC分类号: G01N27/02

    CPC分类号: G01N27/025 G01N27/028

    摘要: A system may include a resonant sensor configured to sense a physical quantity, a measurement circuit communicatively coupled to the resonant sensor and configured to measure one or more resonance parameters associated with the resonant sensor and indicative of the physical quantity using an incident/quadrature detector having an incident channel and a quadrature channel and perform a calibration of a non-ideality between the incident channel and the quadrature channel of the system, the calibration comprising determining the non-ideality by controlling the sensor signal, an oscillation signal for the incident channel, and an oscillation signal for the quadrature channel; and correcting for the non-ideality.

    Frequency-selective common-mode control and output stage biasing in an operational amplifier for a class-D amplifier loop filter

    公开(公告)号:US11522509B2

    公开(公告)日:2022-12-06

    申请号:US17194395

    申请日:2021-03-08

    IPC分类号: H03F3/45

    摘要: An operational amplifier with one or more fully-differential amplifier stages has a common-mode control input. A low-frequency feedback control path is coupled between an output of the fully-differential amplifier stages and the common-mode control input to control low-frequency drift of the common-mode voltage of the output of the stages. A high-frequency feed-forward control path couples a pair of inputs of the stages to control high-frequency ripple of a common-mode voltage of the inputs of the stages. One or more of the differential amplifier stages may have a bias input that controls a direct-current (DC) bias voltage of gates of pull-up transistors of the stage that is both DC and capacitively coupled to the gates so that the stage operates with class A bias at DC and with class AB bias at high frequencies.

    FREQUENCY-SELECTIVE COMMON-MODE CONTROL AND OUTPUT STAGE BIASING IN AN OPERATIONAL AMPLIFIER FOR A CLASS-D AMPLIFIER LOOP FILTER

    公开(公告)号:US20220286098A1

    公开(公告)日:2022-09-08

    申请号:US17194395

    申请日:2021-03-08

    IPC分类号: H03F3/45

    摘要: An operational amplifier with one or more fully-differential amplifier stages has a common-mode control input. A low-frequency feedback control path is coupled between an output of the fully-differential amplifier stages and the common-mode control input to control low-frequency drift of the common-mode voltage of the output of the stages. A high-frequency feed-forward control path couples a pair of inputs of the stages to control high-frequency ripple of a common-mode voltage of the inputs of the stages. One or more of the differential amplifier stages may have a bias input that controls a direct-current (DC) bias voltage of gates of pull-up transistors of the stage that is both DC and capacitively coupled to the gates so that the stage operates with class A bias at DC and with class AB bias at high frequencies.

    Polymorphic playback system with signal detection filters of different latencies

    公开(公告)号:US10726873B2

    公开(公告)日:2020-07-28

    申请号:US16103288

    申请日:2018-08-14

    IPC分类号: G11B27/034 G11B27/19

    摘要: A polymorphic playback system is disclosed in which one or more parameters of a signal path of the polymorphic playback system are varied based on one or more characteristics of a playback signal processed by the signal path, wherein the polymorphic playback system may include a lower-latency detection filter, a higher-latency detection filter, and a control subsystem that uses the lower-latency detection filter for detecting the one or more first characteristics of the playback signal and uses the higher-latency detection filter for detecting the one or more second characteristics of the playback signal.

    Calibration of a dual-path pulse width modulation system

    公开(公告)号:US10181845B1

    公开(公告)日:2019-01-15

    申请号:US15927691

    申请日:2018-03-21

    IPC分类号: H03K7/08 H02M3/157 G06F1/025

    摘要: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.