公开(公告)号：US11112481B2

公开(公告)日：2021-09-07

申请号：US16418710

申请日：2019-05-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Sarang Vadnerkar ,  Vinod Jayakumar

IPC: G01R35/00 ,  H03K5/24 ,  H03G3/20 ,  G01R19/10 ,  H03M1/10 ,  H03M1/00 ,  H02M3/07 ,  H03F3/217

Abstract: An apparatus for calibrating a differential circuit that includes a differential integrator having an input, a gain, and an output connected to a comparator. The differential integrator output is chargeable to a threshold prior to an integration period. The differential integrator integrates the input during the integration period such that the differential integrator output goes toward zero from the threshold. The comparator detects the output of the differential integrator reaching zero. The apparatus includes a closed-loop gain trim circuit to perform a coarse calibration to adjust and set the gain of the differential integrator and a reference generator that generates the threshold to which the differential integrator output is pre-charged. The reference generator is trimmable during a fine calibration to adjust and set the threshold to correct for residual gain error in the differential circuit remaining after the coarse calibration is performed.

公开(公告)号：US10236827B2

公开(公告)日：2019-03-19

申请号：US15622722

申请日：2017-06-14

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Lei Zhu ,  Ku He ,  Xin Zhao ,  Miao Song ,  Saurabh Singh ,  Vinod Jayakumar

IPC: H03F1/02 ,  H03F3/183 ,  H03F3/21 ,  H03F3/217 ,  H03F1/30 ,  H03F1/32 ,  H03F3/187

Abstract: A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.