公开(公告)号：US5953379A

公开(公告)日：1999-09-14

申请号：US606958

申请日：1996-02-23

申请人： Brent A. Myers ,  Paul J. Godfrey

发明人： Brent A. Myers ,  Paul J. Godfrey

IPC分类号： H03C3/09 ,  H03H11/04 ,  H04L27/20 ,  H04L27/06

CPC分类号： H04L27/206 ,  H03C3/0908 ,  H03H11/0472 ,  H03L7/0805

摘要： Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.

公开(公告)号：US5666083A

公开(公告)日：1997-09-09

申请号：US560289

申请日：1995-11-17

申请人： Brent A. Myers ,  Scott G. Bardsley

发明人： Brent A. Myers ,  Scott G. Bardsley

IPC分类号： H03H11/04 ,  H03K5/00 ,  H03F3/45

CPC分类号： H03H11/0422

摘要： A circuit and method for adjusting a cutoff frequency of an active filter, such as a gm-C filter, which has a common mode feedback circuit for providing a bias signal may include plural common base stages having first inputs connected in parallel to a stage of the active filter and second inputs connected in parallel to an output from the common mode feedback circuit, and a capacitor connected to an output from each of the common base stages. The common base stages and their connected capacitors are selectively isolated from the filter output to adjust the cutoff frequency of the filter. The deselected common base stages are also isolated from the common mode feedback circuit and bias generator inputs.

摘要翻译： 用于调节具有用于提供偏置信号的共模反馈电路的有源滤波器（例如gm-C滤波器）的截止频率的电路和方法可以包括多个公共基极级，其具有与第一输入端并联连接的第一输入 有源滤波器和第二输入端并联连接到来自共模反馈电路的输出，以及电容器，连接到每个公共基极级的输出端。 公共基极级及其连接的电容器与滤波器输出选择性隔离以调节滤波器的截止频率。 取消选择的公共基极级也与共模反馈电路和偏置发生器输入隔离。

公开(公告)号：US08330493B2

公开(公告)日：2012-12-11

申请号：US12903782

申请日：2010-10-13

申请人： Brent A. Myers ,  James G. Fox

发明人： Brent A. Myers ,  James G. Fox

IPC分类号： H01L25/00 ,  H03K19/00 ,  H03K19/20

CPC分类号： H03K19/17768 ,  G06F21/755 ,  H01L2924/0002 ,  H03K19/0013 ,  H03K19/0944 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/20 ,  H04L9/001 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12 ,  H01L2924/00

摘要： Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.

摘要翻译： 公开了一种新颖的电路，其能够根据输入逻辑信号产生任何可能的逻辑组合。 该电路被描述为2输入逻辑映射电路，但是可以根据需要扩展到3个或更多个输入。 进一步公开的是具有可变电路拓扑的通用逻辑阵列。 阵列元件中的单元之间的金属化层和/或通孔互连产生实现布尔函数和/或混沌函数和/或逻辑函数的电路拓扑。 新颖的电路为安全应用提供电路拓扑，在控制信号值和输出映射之间没有明显的物理对应关系。 还公开了具有与输入信号状态和输出转换无关的功率签名的网络。 这提供了一个非常有用的电路，用于在安全应用程序中保护数据免受解密功能签名分析。

公开(公告)号：US5736903A

公开(公告)日：1998-04-07

申请号：US637140

申请日：1996-04-24

申请人： Brent A. Myers ,  Scott G. Bardsley

发明人： Brent A. Myers ,  Scott G. Bardsley

IPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/16

CPC分类号： H03L7/0805 ,  H03L7/093 ,  H03L7/099

摘要： Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a pre-mixer tracking filter incorporated into an emitter-coupled logic configured buffer of a carrier frequency generator, using a MOSFET-implemented current-controlled resistance component of a resistor-capacitor network and an associated current control stage. The MOSFET-implemented resistance components of the filter are controlled by the same control current that establishes the carrier generator's output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and effectively independent of process parameters.

摘要翻译： 通过使用MOSFET实现的电流抑制滤波器，通过结合到载波频率发生器的发射极耦合逻辑配置缓冲器中的预混频器跟踪滤波器，实现数据通信系统的杂散能量抑制，而不使用大阶噪声抑制滤波器。 电阻 - 电容网络的受控电阻分量和相关的电流控制级。 滤波器的MOSFET实现的电阻分量由建立载波发生器输出频率的相同控制电流控制。 因此，跟踪滤波器的截止频率与载波成线性比例，并且与工艺参数无关。

公开(公告)号：US5682336A

公开(公告)日：1997-10-28

申请号：US386785

申请日：1995-02-10

申请人： Mojy C. Chian ,  Kevin J. Moye ,  Brent A. Myers

发明人： Mojy C. Chian ,  Kevin J. Moye ,  Brent A. Myers

IPC分类号： G06F17/50 ,  G01R31/28 ,  G06F19/00

CPC分类号： G06F17/5036

摘要： The noise performance of a non-linear circuit design is measured prior to circuit fabrication by a circuit modelling and analysis mechanism, which simulates each noise source as a reduced complexity continuous Gaussian noise waveform. A respective noise source (e.g. thermal or shot) is modelled as a time domain sequence of continuously connected third order polynomial signal waveforms, forming a cubic spline that interconnects successively occurring Gaussian signal amplitude values. For each type of noise source, its associated Gaussian function is determined by the product of the constant multipliers associated with that type of source. The number of points processed for each noise source depends upon the time width of a noise analysis window. Any changes to the noise performance-analyzed circuit design are then effected and the noise performance of the modified circuit is reanalyzed, as necessary, prior to fabrication, thereby ensuring that the operational behavior of the manufactured circuit will meet its intended noise performance specification.

摘要翻译： 非线性电路设计的噪声性能在电路制造之前通过电路建模和分析机制测量，该机制将每个噪声源模拟为复杂度降低的连续高斯噪声波形。 相应的噪声源（例如热或射击）被建模为连续连接的三阶多项式信号波形的时域序列，形成将连续出现的高斯信号幅度值互连的三次样条。 对于每种类型的噪声源，其相关联的高斯函数由与该类型的源相关联的常数乘法器的乘积确定。 每个噪声源处理的点数取决于噪声分析窗口的时间宽度。 然后对噪声性能分析电路设计的任何改变进行，并且在制造之前根据需要重新分析修改的电路的噪声性能，从而确保制造的电路的操作行为将满足其预期的噪声性能规范。

公开(公告)号：US5119321A

公开(公告)日：1992-06-02

申请号：US523020

申请日：1990-05-14

申请人： Willie T. Burton, Jr. ,  Brent A. Myers ,  William W. Wiles, Jr.

发明人： Willie T. Burton, Jr. ,  Brent A. Myers ,  William W. Wiles, Jr.

IPC分类号： H03H11/04

CPC分类号： H03H11/04

摘要： Impulse noise suppression upstream of digital processing circuitry contains a sample and hold mechanism which samples the input signal and stores a plurality of sequential sample values respectively representative of the amplitude of the input signal at successive sample times. The contents of the sample and hold mechanism are compared with an input signal sample to determine whether or not the there are abnormal amplitude variations which potentially constitute impulse noise. In one embodiment the comparison is referenced to the average magnitude of the input signal. In another embodiment the input signal is coupled to a cascaded arrangement of sample and hold circuits which sample and store a plurality of sequential sample values. The time differentials between successive sampling times are such there is little likelihood of occurrences of impulse noise spikes during any two successive sample intervals. The contents of the last sample and hold circuit of the cascaded plurality are compared with the contents of each of selected other sample and hold circuits of the cascaded chain. If the (earliest in time) sampled value stored in the last sampled and hold circuit is determined to be larger (by a system thermal noise offset) than the sampled value of any of the selected samples, then this sample is identified as being a potential noise impulse sample and is prevented from being coupled to downstream processing circuitry. Otherwise it is coupled through a downstream lowpass filter for subsequenty signal analysis.

摘要翻译： 在数字处理电路上游的脉冲噪声抑制包含采样和保持机制，其对输入信号进行采样并存储分别代表输入信号在连续采样时间的幅度的多个顺序采样值。 将采样和保持机制的内容与输入信号样本进行比较，以确定是否存在可能构成脉冲噪声的异常幅度变化。 在一个实施例中，比较参考输入信号的平均幅度。 在另一个实施例中，输入信号耦合到采样和保持电路的级联布置，其采样并存储多个顺序样本值。 在连续采样时间之间的时间差是这样的，所以在任何两个连续采样间隔期间几乎没有发生脉冲噪声尖峰的可能性。 将级联多个的最后采样和保持电路的内容与级联链的所选择的其他采样和保持电路的每个的内容进行比较。 如果存储在最后采样和保持电路中的（最早的时间）采样值被确定为比所选择的任何样本的采样值更大（通过系统热噪声偏移），则该样本被识别为电位 噪声脉冲样本并被阻止与下游处理电路耦合。 否则，它通过下行低通滤波器耦合，用于随后的信号分析。