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1.发明授权Current-controlled carrier tracking filter for improved spurious signal suppression 有权电流控制载波跟踪滤波器，用于改善寄生信号抑制公开(公告)号：US06549590B2
公开(公告)日：2003-04-15
申请号：US09855332
申请日：2001-05-15
申请人： Brent A. Myers , Paul J. Godfrey
发明人： Brent A. Myers , Paul J. Godfrey
IPC分类号： H04L2706
CPC分类号： H04L27/206 , H03C3/0908 , H03H11/0472 , H03L7/0805
摘要： Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.
摘要翻译： 数据通信系统的杂散能量抑制是通过后置混频器跟踪滤波器来实现的，而不需要使用大型的噪声抑制滤波器，该滤波器包含用于跨导电容滤波器的电流控制的MOSFET实现的电阻和相关的跨导调谐级 。 MOSFET实现的电阻由建立输出频率的相同控制电流控制。 结果，跟踪滤波器的截止频率与载波成线性比例，与绝对加工参数和温度无关。
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2.发明授权Current-controlled carrier tracking filter for improved spurious signal suppression 有权电流控制载波跟踪滤波器，用于改善寄生信号抑制公开(公告)号：US06233293B1
公开(公告)日：2001-05-15
申请号：US09334998
申请日：1999-06-17
申请人： Brent A. Myers , Paul J. Godfrey
发明人： Brent A. Myers , Paul J. Godfrey
IPC分类号： H04L2706
CPC分类号： H04L27/206 , H03C3/0908 , H03H11/0472 , H03L7/0805
摘要： Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.
摘要翻译： 数据通信系统的杂散能量抑制是通过后置混频器跟踪滤波器来实现的，而不需要使用大型的噪声抑制滤波器，该滤波器包含用于跨导电容滤波器的电流控制的MOSFET实现的电阻和相关的跨导调谐级 。 MOSFET实现的电阻由建立输出频率的相同控制电流控制。 结果，跟踪滤波器的截止频率与载波成线性比例，与绝对加工参数和温度无关。
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公开(公告)号：US5953379A
公开(公告)日：1999-09-14
申请号：US606958
申请日：1996-02-23
申请人： Brent A. Myers , Paul J. Godfrey
发明人： Brent A. Myers , Paul J. Godfrey
CPC分类号： H04L27/206 , H03C3/0908 , H03H11/0472 , H03L7/0805
摘要： Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.
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公开(公告)号：US5659269A
公开(公告)日：1997-08-19
申请号：US402381
申请日：1995-03-13
申请人： Brent A. Myers
发明人： Brent A. Myers
CPC分类号： H03L7/093 , H03H19/004
摘要： A loop filter for a phase locked loop (PLL) circuit may include two operational amplifiers and switched-capacitors connecting the inverted input and output of the operational amplifiers, the switched-capacitors replacing resistors found in conventional loop filters for PLL circuits. The loop filter may be in a monolithic integrated circuit, and the PLL circuit may operate with a response time heretofore available only with individual (non-IC) components. Phase error due to amplifier offset may be reduced with offset nulling techniques.
摘要翻译： 用于锁相环（PLL）电路的环路滤波器可以包括两个运算放大器和连接运算放大器的反相输入和输出的开关电容器，开关电容器代替用于PLL电路的常规环路滤波器中找到的电阻。 环路滤波器可以在单片集成电路中，并且PLL电路可以以迄今仅可用于单个（非IC）组件的响应时间进行操作。 由于放大器偏移引起的相位误差可能会随着零偏技术而减少。
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公开(公告)号：US4893088A
公开(公告)日：1990-01-09
申请号：US271656
申请日：1988-11-16
IPC分类号： H03F1/30
CPC分类号： H03F1/303
摘要： A transimpedance processor includes a feedback circuit for generating a voltage as a function of the input background level and precharging the capacitor of the input integrator to a negative of the generated voltage in a precharge cycle.
摘要翻译： 跨阻抗处理器包括反馈电路，用于根据输入背景电平产生电压，并且在预充电周期中将输入积分器的电容器预充电到所产生的电压的负值。
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6.发明授权公开(公告)号：US09047746B1
公开(公告)日：2015-06-02
申请号：US12881572
申请日：2010-09-14
CPC分类号： A61B5/4833 , A61B5/0421 , A61B5/065 , A61B5/07 , A61B5/073 , A61B5/14539 , A61B5/42 , A61B2560/0209 , A61B2560/0214 , A61M2205/3592 , G06F19/00 , G06F19/3456 , G06F19/3462 , G08B23/00
摘要： A system and method for monitoring a patient's compliance with a medication regimen includes an electronic tag integral with or attached to a medicine delivery device such as a capsule, the tag having an antenna and a receiver/transmitter, the system also including a reader positioned externally for detecting the presence and location of the delivery device in the patient.
摘要翻译： 用于监测患者对药物治疗程序的依从性的系统和方法包括与药物递送装置如胶囊集成或附接的电子标签，所述标签具有天线和接收器/发射器，所述系统还包括位于外部的读取器 用于检测患者中输送装置的存在和位置。
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公开(公告)号：US07058004B2
公开(公告)日：2006-06-06
申请号：US09864676
申请日：2001-05-24
申请人： Vijay K. Jain , Brent A. Myers
发明人： Vijay K. Jain , Brent A. Myers
IPC分类号： H04J11/00
CPC分类号： H04L27/0004 , H04L27/2601
摘要： An orthogonal wavelet division multiplexing (OWDM) communication system including a synthesis section and a channel interface. The synthesis section includes a filter pair bank with multiple inputs and an output that provides an OWDM signal. Each input receives a corresponding symbol of a supersymbol, where the symbols are from a selected modulation scheme. The synthesis section generates the OWDM signal as a combination of weighted OWDM pulses, where each weighted OWDM pulse represents of a symbol of the supersymbol. An OWDM Spread Spectrum (OWSS) communication system that uses broad-time and broadband pulses generated from a family of OWDM pulses together with a set of orthogonal PN code vectors. The OWSS pulses are mutually orthogonal and allow multi-user operation. Each user is assigned an OWSS pulse corresponding to a particular PN code. OWSS enables high rate operation for wireless channels with the use of an equalizer with FE and DFE sections.
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公开(公告)号：US5572161A
公开(公告)日：1996-11-05
申请号：US497045
申请日：1995-06-30
申请人： Brent A. Myers
发明人： Brent A. Myers
IPC分类号： G05F3/26 , H03H11/12 , H03K19/003 , H03K17/687
CPC分类号： H03K19/00384 , G05F3/262 , H03H11/1282
摘要： A method and circuit for tuning an equivalent resistor in a filter so that the filter is insensitive to temperature changes in which an amplifier output is connected to a common gate of plural MOSFETs for providing equivalent resistances, and in which one input to the amplifier is connected to a reference resistor and the other input to the amplifier is connected to an equivalent resistor that includes one of the plural MOSFETs. An input current to the reference resistor and to the equivalent resistor's MOSFET is inversely proportional to the MOSFET's conduction parameter, k (i.e., .mu.C.sub.ox /2), so that both the inputs to the amplifier vary to change the amplifier output voltage to the common gate. The amplifier output changes render the filter insensitive to temperature changes.
摘要翻译： 一种用于调整滤波器中的等效电阻器的方法和电路，使得滤波器对温度变化不敏感，其中放大器输出连接到用于提供等效电阻的多个MOSFET的公共栅极，并且其中连接到放大器的一个输入端 到参考电阻器，并且放大器的另一个输入端连接到包括多个MOSFET之一的等效电阻器。 到参考电阻和等效电阻的MOSFET的输入电流与MOSFET的导通参数k（即，μCox / 2）成反比，使得放大器的输入变化，以将放大器输出电压改变为公共 门。 放大器输出变化使过滤器对温度变化不敏感。
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公开(公告)号：US4616145A
公开(公告)日：1986-10-07
申请号：US595738
申请日：1984-04-02
申请人： Brent A. Myers
发明人： Brent A. Myers
CPC分类号： H03F3/45479 , H03F1/303
摘要： A CMOS limiter with input hysteresis, responsive to an input signal of varying amplitude, produces an output signal which changes between at least first and second levels, the transitions occurring when the absolute value of the amplitude of the input signal exceeds predetermined reference level. The limiter is fabricated on a single integrated circuit using CMOS switched capacitor techniques. An SC switching array selects between sampled input signal and an inverted sampled input signal depending upon the value of the output signal produced by the limiter. A comparing network (comprising an active CMOS comparator responsive to a difference signal produced at a summing node) changes the level of the output signal of the limiter when the selected signal exceeds a predetermined reference value. The summing node includes a signal level storing device (i.e. a precision capacitor) for storing the reference level during the period in which the input signal is sampled. The input offset voltage of the comparator is subtracted from the selected signal to reduce the output error of the comparator due to non-zero input offset voltage. The limiter includes a clock signal generator and sequential logic responsive to the clock signal generator for synchronizing the switching of the various switched capacitor switching elements in order to provide hysteresis.
摘要翻译： 具有响应于变化幅度的输入信号的输入滞后的CMOS限制器产生在至少第一和第二电平之间变化的输出信号，当输入信号的幅度的绝对值超过预定参考电平时发生转换。 使用CMOS开关电容器技术在单个集成电路上制造限幅器。 SC开关阵列根据由限幅器产生的输出信号的值，在采样输入信号和反相采样输入信号之间进行选择。 当所选择的信号超过预定参考值时，比较网络（包括响应于在求和节点产生的差分信号的有源CMOS比较器）改变限幅器的输出信号的电平。 求和节点包括用于在输入信号被采样的时段期间存储参考电平的信号电平存储装置（即精密电容器）。 从选择的信号中减去比较器的输入失调电压，以减少由于非零输入失调电压引起的比较器的输出误差。 限幅器包括响应于时钟信号发生器的时钟信号发生器和顺序逻辑器，用于同步各种开关电容器开关元件的开关以提供迟滞。
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10.发明授权公开(公告)号：US06405022B1
公开(公告)日：2002-06-11
申请号：US09572417
申请日：2000-05-17
IPC分类号： H04B140
摘要： A radio frequency transceiver includes a radio frequency processor having a modulator/demodulator phase locked loop circuit for generating a second intermediate frequency signal. A heterodyne frequency translation loop circuit receives the second intermediate frequency signal and outputs a first intermediate frequency signal. A transmit mixer receives the first intermediate frequency signal and outputs a transmit radio frequency signal fo. A synthesizer circuit is operatively connected to the transmit mixer and the heterodyne frequency translation loop circuit for generating an oscillation signal to the transmit mixer and the heterodyne frequency translation loop circuit. The oscillation signal is divided down by factor N before passing into the heterodyne frequency translation loop circuit.
摘要翻译： 射频收发机包括具有用于产生第二中频信号的调制器/解调器锁相环电路的射频处理器。 外差频平移环路接收第二中频信号并输出第一中频信号。 发送混合器接收第一中频信号并输出发射射频信号fo。 合成器电路可操作地连接到发射混频器和外差频率转换环路电路，用于向发射混频器和外差频率平移环路产生振荡信号。 在通过外差频平移环路电路之前，将振荡信号除以因子N.
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