公开(公告)号：US10083988B2

公开(公告)日：2018-09-25

申请号：US14429165

申请日：2014-06-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaodi Liu ,  Gang Wang

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1214 ,  H01L27/1233 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/786 ,  H01L29/78696

Abstract: The present invention provides a complementary thin film transistor and a manufacturing method thereof, an array substrate and a display apparatus, relates to the field of manufacturing technology of thin film transistor, and can solve the problem that active layer materials of first and second thin film transistors in a complementary thin film transistor of the prior art have influence with each other. The manufacturing method of the present invention comprises steps of: forming a pattern comprising an active layer of a first thin film transistor and a protective layer on a base by a patterning process, and the protective layer is at least located above the active layer of the thin film transistor; and forming a pattern of an active layer of a second thin film transistor on the base subjected to above step by a patterning process. The present invention may be applied to various circuits and systems.

公开(公告)号：US20170033131A1

公开(公告)日：2017-02-02

申请号：US14908652

申请日：2015-09-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaodi Liu ,  Gang Wang

IPC: H01L27/12

CPC classification number: H01L27/1255 ,  H01L27/1288

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises a gate electrode layer, an active layer and a source-drain electrode layer that are disposed on a substrate. The substrate comprises a storage capacitance region thereon II. In the storage capacitance region II, projections of the gate electrode layer and the active layer on the substrate are at least partially overlapped, and projections of the active layer and the source-drain electrode layer on the substrate are at least partially overlapped. The array substrate can effectively increase the storage capacitance without increasing an area occupied by the storage capacitance region, which is advantageously to reduce a pixel area and increase PPI.

Abstract translation: 公开了阵列基板，其制造方法和显示装置。 阵列基板包括设置在基板上的栅极电极层，有源层和源极 - 漏极电极层。 衬底包括其上的存储电容区域。 在存储电容区域II中，基板上的栅电极层和有源层的突起至少部分重叠，并且基板上的有源层和源极 - 漏极电极层的突起至少部分重叠。 阵列基板可以有效地增加存储电容，而不增加存储电容区域占用的面积，这有利于减少像素面积并增加PPI。

公开(公告)号：US20160011158A1

公开(公告)日：2016-01-14

申请号：US14574841

申请日：2014-12-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaodi Liu ,  Cuili Gai ,  Fengjuan Liu ,  Gang Wang

IPC: G01N33/00 ,  H05B3/03 ,  H01L29/26 ,  H01L29/22 ,  H01L29/786

CPC classification number: G01N33/0027 ,  G01N33/0062 ,  H01L29/22 ,  H01L29/26 ,  H01L29/786

Abstract: Embodiments of the present invention provide a gas detection sensor, a display panel, and a display device. The gas detection sensor comprises: a gas sensitive part; two detection electrodes electrically connected with each other through the gas sensitive part; and a protective layer enclosing the gas sensitive part and the detection electrodes. When one of the detection electrodes is applied with a detecting signal, the detecting signal is output from the other detection electrode after being modulated by the gas sensitive part, and a voltage signal output by the other detection electrode is related to a nature of the outside air to which the gas sensitive part is exposed, thereby a detection on air quality may be achieved through detecting the voltage signal output from the other detection electrode, such that a simply structured and portable gas detection sensor can be realized.

Abstract translation: 本发明的实施例提供一种气体检测传感器，显示面板和显示装置。 气体检测传感器包括：气体敏感部件; 两个检测电极通过气体敏感部分彼此电连接; 以及包围气体敏感部分和检测电极的保护层。 当检测电极中的一个被施加检测信号时，在被气体敏感部分调制之后，从另一检测电极输出检测信号，并且由另一个检测电极输出的电压信号与外部的性质有关 可以通过检测从其他检测电极输出的电压信号来实现空气质量的检测，从而可以实现简单结构化的便携式气体检测传感器。

公开(公告)号：US10804298B2

公开(公告)日：2020-10-13

申请号：US16721109

申请日：2019-12-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaodi Liu ,  Guangcai Yuan ,  Gang Wang

IPC: H01L27/12 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  G02F1/1345 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32

Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate, and a first conductive layer and a second conductive layer which are sequentially disposed on the base substrate, and at least two passivation layers are continuously arranged between the first conductive layer and the second conductive layer in a direction perpendicular to the base substrate.

公开(公告)号：US20200127018A1

公开(公告)日：2020-04-23

申请号：US16721109

申请日：2019-12-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaodi Liu ,  Guangcai Yuan ,  Gang Wang

IPC: H01L27/12 ,  H01L23/31 ,  G02F1/1368 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/1345 ,  H01L21/441 ,  H01L21/02 ,  H01L29/66 ,  H01L23/00 ,  H01L23/29 ,  H01L27/32

Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate, and a first conductive layer and a second conductive layer which are sequentially disposed on the base substrate, and at least two passivation layers are continuously arranged between the first conductive layer and the second conductive layer in a direction perpendicular to the base substrate.

公开(公告)号：US10186527B2

公开(公告)日：2019-01-22

申请号：US15545817

申请日：2016-04-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong Kong ,  Jun Cheng ,  Xiaodi Liu

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/12 ,  H01L27/12 ,  H01L21/77 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

Abstract: The embodiments of present disclosure disclose an array substrate, a method for manufacturing the array substrate, and a display device. The method includes forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.

公开(公告)号：US20170187001A1

公开(公告)日：2017-06-29

申请号：US15303009

申请日：2016-04-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jingang Fang ,  Xiaodi Liu ,  Dongfang Wang ,  Lungpao Hsin

IPC: H01L51/52 ,  H01L51/56 ,  H01L27/32

CPC classification number: H01L51/5265 ,  H01L27/3211 ,  H01L27/3244 ,  H01L51/5215 ,  H01L51/5218 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/305 ,  H01L2251/308 ,  H01L2251/558

Abstract: The present application discloses a light emitting diode comprising a plurality of sub-pixels comprising a first electrode layer, wherein the first electrode layer is a reflective electrode layer; a second electrode layer; a light emitting layer between the first electrode layer and the second electrode layer; a first microcavity tuning layer sandwiched by the first electrode layer and the light emitting layer within the plurality of sub-pixels; and a second microcavity tuning layer sandwiched by the first microcavity tuning layer and the light emitting layer within at least one of the plurality of sub-pixels, and the first microcavity tuning layer is sandwiched by the first electrode layer and the second microcavity tuning layer within the at least one of the plurality of sub-pixels. The first microcavity tuning layer is made of a material including a transparent conductive material in a first state and the second microcavity tuning layer is made of a material including a transparent conductive material in a second state, the first state and the second state are different states selected from a crystalline state and an amorphous state.