公开(公告)号：US10949292B1

公开(公告)日：2021-03-16

申请号：US16594223

申请日：2019-10-07

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Michael Andrew Campbell ,  Alexander Alfred Hornung ,  Alex James Waugh ,  Klas Magnus Bruce ,  Richard Roy Grisenthwaite

IPC: G06F11/20 ,  G11C29/08 ,  G06F11/10 ,  G11C29/18 ,  G06F11/30

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

公开(公告)号：US10855609B2

公开(公告)日：2020-12-01

申请号：US16269740

申请日：2019-02-07

Applicant: Arm Limited

Inventor： Geoffray Matthieu Lacourba ,  Alex James Waugh

IPC: H04L12/437 ,  H04L12/801 ,  H04L12/933

Abstract: An interconnect is provided that has a plurality of nodes, and a ring network to which each of the nodes is connected to allow packets to be transmitted between nodes. For an ordered sequence of packets one of the nodes is arranged as a source node to add each packet of the ordered sequence on to the ring network, and another of the nodes is arranged as a destination node to remove each packet of the ordered sequence from the ring network. The source node is enabled to add a packet of the ordered sequence on to the ring network without waiting for a previously added packet of the ordered sequence to be removed from the ring network by the destination node. When the destination node is unable to accept a given packet of the ordered sequence that is currently being presented to the destination node by the ring network, that given packet remains on the ring network and continues to be transmitted around the ring network such that after a respin period that given packet will be presented again to the destination node. The destination node is then arranged to prevent acceptance of at least any other packets of the ordered sequence subsequently presented to the destination node by the ring network until the destination node has accepted the given packet following at least one respin period. This can improve the efficiency of the ring network in the handling of ordered sequences of packets, whilst still ensuring the ordering constraints are met.

公开(公告)号：US10802969B2

公开(公告)日：2020-10-13

申请号：US16266185

申请日：2019-02-04

Applicant: Arm Limited

Inventor： Alex James Waugh ,  Geoffray Matthieu Lacourba

IPC: G06F12/0815 ,  H04L12/747 ,  G06F12/0862 ,  G06F12/0811

Abstract: An interconnect, and method of operation of such an interconnect, are disclosed. The interconnect has a plurality of nodes, and a routing network via which information is routed between the plurality of nodes. The plurality of nodes comprises at least one slave node used to couple master devices to the interconnect, at least one master node used to couple slave devices to the interconnect, and at least one control node. Each control node is responsive to a slave node request received via the routing network from a slave node, to perform an operation to service the slave node request and, when a propagation condition is present, to issue a control node request via the routing network to a chosen master node in order to service the slave node request. The chosen master node processes the control node request in order to generate a master node response, and treats as a default destination for the master node response the control node that issued the control node request. In response to a trigger event occurring after the control node request has been issued, the control node sends an update destination request to the chosen master node that identifies a replacement destination node for the master node response. At least in the absence of an override condition, the chosen master node then sends the master node response via the routing network to the replacement destination node.

公开(公告)号：US10754743B2

公开(公告)日：2020-08-25

申请号：US16221785

申请日：2018-12-17

Applicant: Arm Limited

Inventor： Alex James Waugh ,  Pedro López Muñoz ,  Peng Wang

IPC: G06F11/22 ,  G06F11/36 ,  G01R31/317 ,  G06F16/903 ,  G06F11/30 ,  G06F11/26

Abstract: At least one processor core has debug and non-debug modes of operation. Debug control circuitry controls operation of the at least one processor core when in the debug mode. On power up of a given processor core, the core checks a debug status value stored in a debug status storage element. When the debug status value has a first value, a debug connect sequence of messages is exchanged with the debug control circuitry over a debug interface to determine whether the given processor core should operate in the debug mode or the non-debug mode, and the debug status value is set to a second value when it is determined that the given processor core should operate in the non-debug mode. When the debug status value has the second value, the given processor core omits initiating the debug connect sequence and determines that it should operate in the non-debug mode.

公开(公告)号：US20250103129A1

公开(公告)日：2025-03-27

申请号：US18474400

申请日：2023-09-26

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Munish Kumar ,  Vivek Asthana ,  Andrew John Turner ,  Alex James Waugh

IPC: G06F1/3296 ,  G06F12/0815

Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

公开(公告)号：US11784941B2

公开(公告)日：2023-10-10

申请号：US17374142

申请日：2021-07-13

Applicant: Arm Limited

Inventor： Alex James Waugh ,  Andrew John Turner ,  Shobhit Singhal

IPC: H04L47/762 ,  H04L47/78 ,  H04L12/42 ,  H04L47/122

CPC classification number: H04L47/762 ,  H04L12/42 ,  H04L47/122 ,  H04L47/781 ,  H04L2012/421

Abstract: An apparatus and method for operating a ring interconnect are disclosed. The ring interconnect has a plurality of nodes that are used to connect to associated components, and is arranged to transport a plurality of slots around the ring interconnect between the nodes in order to transfer items of traffic allocated into those slots between components connected to the nodes. For each item of traffic, one of the components acts as a source to allocate that item of traffic into a slot, and another components acts as destination to seek to remove that item of traffic from the slot. In a default mode of operation, the ring interconnect is arranged to allow all of the slots to be available for transfer of any items of traffic. Special slot management circuitry is provided that is responsive to a throughput alert trigger indicating a potential for occurrence of a throughput inhibiting condition, to cause a slot amongst the plurality of slots to be reserved as a special slot that is constrained for use only when one or more determined conditions are met. Further, the one or more determined conditions are arranged to cause the special slot to be used in a manner that seeks to avoid the throughput inhibiting condition arising.

公开(公告)号：US11200177B2

公开(公告)日：2021-12-14

申请号：US16327501

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Alex James Waugh ,  Dimitrios Kaseridis ,  Klas Magnus Bruce ,  Michael Filippo ,  Joseph Michael Pusdesris ,  Jamshed Jalal

IPC: G06F12/00 ,  G06F12/121 ,  G06F12/0815

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

公开(公告)号：US10969993B2

公开(公告)日：2021-04-06

申请号：US16521723

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Andrew John Turner ,  Alex James Waugh ,  Geoffray Lacourba ,  Fergus Wilson MacGarry

IPC: G06F13/00 ,  G06F3/06

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

公开(公告)号：US10691511B2

公开(公告)日：2020-06-23

申请号：US16135335

申请日：2018-09-19

Applicant: Arm Limited

Inventor： Fergus Wilson MacGarry ,  Alex James Waugh

IPC: G06F9/54 ,  G06F11/34

Abstract: A first event source generates a first indication of a first event which has occurred in the first event source, the first indication being one of a predefined set of indications corresponding to a plurality of event types. A second event source generates a second indication of a second event which has occurred in the second event source, the second indication being one of the predefined set of indications corresponding to the plurality of event types. First event selection circuitry responds to the first indication matching a selected event type of the plurality of event types to generate a first count signal and second event selection circuitry responds to the second indication matching the selected event type of the plurality of event types to generate a second count signal. Count circuitry increments a counter in response to either the first count signal or the second count signal.

公开(公告)号：US10216218B2

公开(公告)日：2019-02-26

申请号：US15227051

申请日：2016-08-03

Applicant: ARM LIMITED

Inventor： Alex James Waugh

IPC: G06F1/12 ,  G06F1/26

Abstract: An apparatus includes control circuitry configured to receive a first N-bit count value in a first domain, and to determine an M-bit increment indicating value based on the first N-bit count value and a reference value, where M