公开(公告)号：US10754743B2

公开(公告)日：2020-08-25

申请号：US16221785

申请日：2018-12-17

Applicant: Arm Limited

Inventor： Alex James Waugh ,  Pedro López Muñoz ,  Peng Wang

IPC: G06F11/22 ,  G06F11/36 ,  G01R31/317 ,  G06F16/903 ,  G06F11/30 ,  G06F11/26

Abstract: At least one processor core has debug and non-debug modes of operation. Debug control circuitry controls operation of the at least one processor core when in the debug mode. On power up of a given processor core, the core checks a debug status value stored in a debug status storage element. When the debug status value has a first value, a debug connect sequence of messages is exchanged with the debug control circuitry over a debug interface to determine whether the given processor core should operate in the debug mode or the non-debug mode, and the debug status value is set to a second value when it is determined that the given processor core should operate in the non-debug mode. When the debug status value has the second value, the given processor core omits initiating the debug connect sequence and determines that it should operate in the non-debug mode.

公开(公告)号：US10922082B2

公开(公告)日：2021-02-16

申请号：US16292534

申请日：2019-03-05

Applicant: Arm Limited

Inventor： Matthew Lee Winrow ,  Peng Wang

IPC: G06F9/38

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions fetched from an instruction cache, an instruction prefetcher to speculatively prefetch instructions into the instruction cache, and a branch predictor having at least one branch prediction structure to store branch prediction data for predicting at least one branch property of an instruction fetched for processing by the processing circuitry. On prefetching of a given instruction into the instruction cache by the instruction prefetcher, the branch predictor is configured to perform a prefetch-triggered update of the branch prediction data based on information derived from the given instruction prefetched by the instruction prefetcher. This can help to improve performance, especially for workloads with a high branch density and large branch re-reference interval.