公开(公告)号：US11777869B2

公开(公告)日：2023-10-03

申请号：US16170366

申请日：2018-10-25

Applicant: Arm Limited

Inventor： Fergus Wilson MacGarry ,  Alex James Waugh ,  Andrew John Turner

IPC: H04B10/275 ,  H04L47/783 ,  H04L41/0896 ,  H04L47/30 ,  H04L41/0806 ,  H04J3/16 ,  H04J3/08 ,  H04B10/2575 ,  H04L12/437 ,  H04L49/102 ,  H04J3/14 ,  H04L47/10

CPC classification number: H04L47/783 ,  H04B10/25755 ,  H04B10/275 ,  H04J3/085 ,  H04J3/167 ,  H04L12/437 ,  H04L41/0806 ,  H04L41/0896 ,  H04L47/30 ,  H04L49/102 ,  H04J3/14 ,  H04L47/13

Abstract: A ring interconnect system comprises a plurality of nodes. Each node is connected to two other nodes to form a ring interconnect. Every pair of nodes is connected by an inter-node path for that pair of nodes distinct from the ring interconnect. Each of the nodes comprises a message buffer to buffer messages received from at least one device associated with the node. Each of the nodes also comprises activity level circuitry to transmit an activity indication, when a number of the messages in the message buffer is equal to or above a threshold, to each other node of the plurality of nodes via the respective inter-node paths. Each of the nodes also comprises arbitrator circuitry to receive the activity indications from each other node and from the activity level circuitry, and to allow ingress of a message from the message buffer onto the ring interconnect in dependence on the activity indications. Also provided is a method of operating a node of a ring interconnect system.

公开(公告)号：US11314648B2

公开(公告)日：2022-04-26

申请号：US15427421

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Kias Magnus Bruce ,  Alex James Waugh ,  Geoffray Lacourba ,  Paul Gilbert Meyer ,  Bruce James Mathewson ,  Phanindra Kumar Mannava

IPC: G06F12/0862 ,  G06F12/0831 ,  G06F12/0811 ,  G06F15/78 ,  G06F11/34

Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

公开(公告)号：US11036279B2

公开(公告)日：2021-06-15

申请号：US16397025

申请日：2019-04-29

Applicant: Arm Limited

Inventor： Alex James Waugh

IPC: G06F1/32 ,  G06F1/3287 ,  G06F12/0895 ,  G06F1/3234 ,  G06F1/28

Abstract: An apparatus and method are provided for managing a cache. The cache is arranged to comprise a plurality of cache sections, where each cache section is powered independently of the other cache sections in the plurality of cache sections, and the apparatus has power control circuitry to control power to each of the cache sections. The power control circuitry is responsive to a trigger condition indicative of an ability to operate the cache in a power saving mode, to perform a latency evaluation process to determine a latency indication for each of the cache sections, and to control which of a subset of the cache sections to power off in dependence on the latency indication. This can allow the power consumption savings realised by turning off one or more cache sections to be optimised to take into account the current system state.

公开(公告)号：US11016902B2

公开(公告)日：2021-05-25

申请号：US16382394

申请日：2019-04-12

Applicant: Arm Limited

Inventor： Geoffray Matthieu Lacourba ,  Andrew John Turner ,  Alex James Waugh

IPC: G06F12/0868 ,  G06F13/14 ,  G06F13/38

Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.

公开(公告)号：US10248572B2

公开(公告)日：2019-04-02

申请号：US15271611

申请日：2016-09-21

Applicant: ARM Limited

Inventor： Jose Gonzalez Gonzalez ,  Alex James Waugh ,  Adnan Khan

IPC: G06F12/0895 ,  G06F12/1045 ,  G06F12/0831

Abstract: An apparatus and method are provided for operating a virtually indexed, physically tagged cache. The apparatus has processing circuitry for performing data processing operations on data, and a virtually indexed, physically tagged cache for storing data for access by the processing circuitry. The cache is accessed using a virtual address portion of a virtual address in order to identify a number of cache entries, and then physical address portions stored in those cache entries are compared with the physical address derived from the virtual address in order to detect whether a hit condition exists. Further, snoop request processing circuitry is provided that is responsive to a snoop request specifying a physical address, to determine a plurality of possible virtual address portions for the physical address, and to perform a snoop processing operation in order to determine whether the hit condition is detected for a cache entry when accessing the cache storage using the plurality of possible virtual address portions. On detection of the hit condition a coherency action is performed in respect of the cache entry causing the hit condition. This allows effective detection and removal of aliasing conditions that can arise when different virtual addresses associated with the same physical address cause cache entries in different sets of the cache to be accessed.

公开(公告)号：US10061728B2

公开(公告)日：2018-08-28

申请号：US14801990

申请日：2015-07-17

Applicant: ARM LIMITED

Inventor： Alex James Waugh

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F9/50 ,  G06F13/1663 ,  G06F13/4031 ,  G06F13/4282

Abstract: A device for selecting requests to be serviced in a data processing apparatus has an arbitration stage for selecting an arbitrated request from a plurality of candidate requests and a hazard detection stage for performing hazard detection to predict whether the arbitrated request selected by the arbitration stage meets a hazard condition. If the arbitrated request meets the hazard condition, the hazard detection stage returns the arbitration request to the arbitration stage for a later arbitration and sets a hazard indication for the returned request. Also, the hazard detection stage controls at least one other arbitration request to be returned if it conflicts with a candidate request having the hazard indication set. This approach prevents denial of service to requests that were hazarded.

公开(公告)号：US11334486B2

公开(公告)日：2022-05-17

申请号：US16305165

申请日：2017-04-27

Applicant: ARM LIMITED

Inventor： Adnan Khan ,  Alex James Waugh ,  Jose Gonzalez-Gonzalez

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0817 ,  G06F12/0831

Abstract: An apparatus (300) for processing data comprises a plurality of memory access request sources (102,104) which generate memory access requests. Each of the memory access request sources has a local memory (106,108), and the apparatus also includes a shared memory (110). When the memory access requests are atomic memory access requests, contention may arise over common data. When this occurs, the present technique triggers a switch of processing data in the local memory of a memory access request source to processing data in the shared memory.

公开(公告)号：US11256623B2

公开(公告)日：2022-02-22

申请号：US15427459

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Michael Filippo ,  Paul Gilbert Meyer ,  Alex James Waugh ,  Geoffray Matthieu Lacourba

IPC: G06F12/0831 ,  G06F12/0808

Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

公开(公告)号：US11055250B2

公开(公告)日：2021-07-06

申请号：US16593127

申请日：2019-10-04

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Klas Magnus Bruce ,  Damien Guillaume Pierre Payet ,  Jamshed Jalal ,  Alex James Waugh

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16

Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

公开(公告)号：US10691606B2

公开(公告)日：2020-06-23

申请号：US15392190

申请日：2016-12-28

Applicant: ARM Limited

Inventor： Davide Marani ,  Alex James Waugh

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0864 ,  G06F12/1027

Abstract: An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups. The first mapping and the second mapping are selected so as to prevent application of a cache feature to the way groups by one of the cache feature circuits from interfering with the ability of the other cache feature circuit to access at least one cache way in each of the way groups. Such an approach alleviates the risk of actions taken by one of the cache features from interfering with the ability of the other cache feature to operate as intended.