公开(公告)号：US20140273312A1

公开(公告)日：2014-09-18

申请号：US14199318

申请日：2014-03-06

Applicant: APPLIED MATERIALS, INC.

Inventor： Dong-Kil YIM ,  Tae Kyung WON ,  Seon-Mee CHO

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/24

Abstract: The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer.

Abstract translation: 本发明一般涉及测量针孔确定的方法。 一方面，提供了一种测量堆叠中的针孔的方法，例如TFT堆叠。 该方法可以包括在衬底的沉积表面上形成有源层，在有源层上形成电介质层，向至少介电层递送蚀刻剂，以蚀刻电介质层和在其中形成的任何针孔，并光学测量 使用有源层的蚀刻介电层的针孔密度。

公开(公告)号：US20190214447A1

公开(公告)日：2019-07-11

申请号：US16243314

申请日：2019-01-09

Applicant: Applied Materials, Inc.

Inventor： Jung Bae KIM ,  Dong-Kil YIM ,  Soo Young CHOI ,  Lai ZHAO

IPC: H01L27/32 ,  G09G3/3233

CPC classification number: H01L27/3265 ,  G09G3/3233 ,  G09G2300/0465 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/3262 ,  H01L27/3272

Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

公开(公告)号：US20180261698A1

公开(公告)日：2018-09-13

申请号：US15456418

申请日：2017-03-10

Applicant: Applied Materials, Inc.

Inventor： Rodney Shunleong LIM ,  Dong-Kil YIM

IPC: H01L29/786 ,  H01L29/207 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66 ,  H01L21/423 ,  H01L29/20 ,  H01L21/223

CPC classification number: H01L29/7869 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/423 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78681

Abstract: Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

公开(公告)号：US20170229554A1

公开(公告)日：2017-08-10

申请号：US15198955

申请日：2016-06-30

Applicant: Applied Materials, Inc.

Inventor： Soo Young CHOI ,  Jrjyan Jerry CHEN ,  Dong-Kil YIM ,  Xiangxin RUI

IPC: H01L29/49 ,  H01L49/02 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/4908 ,  G02F1/136213 ,  G02F1/1368 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L28/40 ,  H01L28/60 ,  H01L2227/323

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure includes source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is a high-k material having a dielectric constant greater than 10, and a gate electrode formed above or below the gate insulating layer.

公开(公告)号：US20170229490A1

公开(公告)日：2017-08-10

申请号：US15411724

申请日：2017-01-20

Applicant: Applied Materials, Inc.

Inventor： Xuena ZHANG ,  Dong-Kil YIM ,  Wenqing DAI ,  Harvey YOU ,  Tae Kyung WON ,  Hsiao-Lin YANG ,  Wan-Yu LIN ,  Yun-chu TSAI

IPC: H01L27/12 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L29/4908 ,  G02F1/136213 ,  G02F1/1368 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L28/40 ,  H01L28/60 ,  H01L2227/323

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

公开(公告)号：US20170133492A1

公开(公告)日：2017-05-11

申请号：US15412519

申请日：2017-01-23

Applicant: Applied Materials, Inc.

Inventor： Jrjyan Jerry CHEN ,  Soo Young CHOI ,  Dong-Kil YIM ,  Yan YE

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L29/78606 ,  H01L29/7869

Abstract: The present invention generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises IGZO or zinc oxide. After the source and drain electrodes are formed, but before the passivation layers or etch stop layers are deposited thereover, the active channel is exposed to an N2O or O2 plasma. The interface between the active channel and the passivation layers or etch stop layers are either altered or damaged during formation of the source and drain electrodes. The N2O or O2 plasma alters and repairs the interface between the active channel and the passivation or etch stop layers.