公开(公告)号：US20180218905A1

公开(公告)日：2018-08-02

申请号：US15884129

申请日：2018-01-30

Applicant: Applied Materials, Inc.

Inventor： Beom Soo PARK ,  Dongsuh LEE ,  Hsiao-Lin YANG ,  Fu-Ting CHANG ,  Hsiang AN ,  Tsung-Yao SU

IPC: H01L21/205 ,  H01L21/02 ,  C23C16/505 ,  C23C16/517 ,  C23C16/44 ,  C23C16/455 ,  C23C8/36

CPC classification number: H01L21/205 ,  C23C8/36 ,  C23C16/4405 ,  C23C16/455 ,  C23C16/4586 ,  C23C16/505 ,  C23C16/517 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/68742 ,  H01L21/68757

Abstract: A method and apparatus for equalized plasma coupling is provided herein. Discontinuity marks, also known as golf tee mura, are eliminated or minimized by biasing or grounding lift pins disposed in openings towards the center of a substrate support. To prevent shorting between a biased or grounded lift pin and the substrate support, lift pins are electrically isolated from the substrate support. The electrical isolation of the lift pin includes coating the lift pins with an electrically insulating material or lining a respective substrate support opening with an electrically insulating material.

公开(公告)号：US20170229490A1

公开(公告)日：2017-08-10

申请号：US15411724

申请日：2017-01-20

Applicant: Applied Materials, Inc.

Inventor： Xuena ZHANG ,  Dong-Kil YIM ,  Wenqing DAI ,  Harvey YOU ,  Tae Kyung WON ,  Hsiao-Lin YANG ,  Wan-Yu LIN ,  Yun-chu TSAI

IPC: H01L27/12 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L29/4908 ,  G02F1/136213 ,  G02F1/1368 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L28/40 ,  H01L28/60 ,  H01L2227/323

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.