公开(公告)号：US20160085550A1

公开(公告)日：2016-03-24

申请号：US14491149

申请日：2014-09-19

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Richard F. Russo ,  Ronald P. Hall ,  Conrado Blasco

IPC: G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F9/38

CPC classification number: G06F12/1045 ,  G06F9/324 ,  G06F9/3804 ,  G06F9/382 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

Abstract: A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

Abstract translation: 一种有效指示分支目标地址的系统和方法。 在将指令安装到指令高速缓存之前，半导体芯片预先对计算机程序的指令进行解码。 响应于确定特定指令是具有相对于程序计数器地址（PC）的位移的控制流程指令，芯片用目标地址的子集替换特定指令中的PC相对位移的一部分。 目标地址的子集是完整目标地址的非翻译物理子集。 当重新编码的特定指令被取出和解码时，PC相对位移的剩余部分被添加到用于获取特定指令的PC的虚拟部分。 结果与嵌入在获取的特定指令中的目标地址的部分连接以形成完整的目标地址。

公开(公告)号：US20150169041A1

公开(公告)日：2015-06-18

申请号：US14104042

申请日：2013-12-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/3802 ,  G06F9/3806 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

Abstract translation: 处理器包括用于禁用分支预测单元的存储器阵列的机构。 处理器可以包括可以包括多个条目的下一个提取预测单元。 每个条目可以对应于下一个指令获取组，并且可以存储对应的下一个提取组是否包括条件分支指令的指示。 响应于下一个提取组不包括条件分支指令的指示，获取预测单元可以被配置为在下一个指令执行周期中禁止分支预测单元的存储器阵列。

公开(公告)号：US20150039860A1

公开(公告)日：2015-02-05

申请号：US13955847

申请日：2013-07-31

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Conrado Blasco-Allue

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3863

Abstract: A system and method for efficiently performing microarchitectural checkpointing. A register rename unit within a processor determines whether a physical register number qualifies to have duplicate mappings. Information for maintenance of the duplicate mappings is stored in a register duplicate array (RDA). To reduce the penalty for misspeculation or exception recovery, control logic in the processor supports multiple checkpoints. The RDA is one of multiple data structures to have checkpoint copies of state. The RDA utilizes a content addressable memory (CAM) to store physical register numbers. The duplicate counts for both the current state and the checkpoint copies for a given physical register number are updated when instructions utilizing the given physical register number are retired. To reduce on-die real estate and power consumption, a single CAM entry is stores the physical register number and the other fields are stored in separate storage elements.

Abstract translation: 一种有效执行微架构检查点的系统和方法。 处理器内的寄存器重命名单元确定物理寄存器号码是否有资格具有重复的映射。 用于维护重复映射的信息存储在寄存器重复数组（RDA）中。 为了减少错误或异常恢复的处罚，处理器中的控制逻辑支持多个检查点。 RDA是具有状态检查点副本的多个数据结构之一。 RDA利用内容可寻址存储器（CAM）来存储物理寄存器编号。 对于给定的物理寄存器号码的当前状态和检查点副本的重复计数将在使用给定物理寄存器号码的指令退出时更新。 为了降低裸片上的不动产和功耗，单个CAM条目存储物理寄存器号，其他字段存储在单独的存储元件中。

公开(公告)号：US11068271B2

公开(公告)日：2021-07-20

申请号：US14444798

申请日：2014-07-28

Applicant: Apple Inc.

Inventor： Shyam Sundar

IPC: G06F9/38 ,  G06F9/30

Abstract: A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction qualifies for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

公开(公告)号：US20190286218A1

公开(公告)日：2019-09-19

申请号：US16363517

申请日：2019-03-25

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F1/3237 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/324 ,  G06F9/38

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

公开(公告)号：US09311084B2

公开(公告)日：2016-04-12

申请号：US13955847

申请日：2013-07-31

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Conrado Blasco-Allue

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30032 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3863

Abstract: A system and method for efficiently performing microarchitectural checkpointing. A register rename unit within a processor determines whether a physical register number qualifies to have duplicate mappings. Information for maintenance of the duplicate mappings is stored in a register duplicate array (RDA). To reduce the penalty for misspeculation or exception recovery, control logic in the processor supports multiple checkpoints. The RDA is one of multiple data structures to have checkpoint copies of state. The RDA utilizes a content addressable memory (CAM) to store physical register numbers. The duplicate counts for both the current state and the checkpoint copies for a given physical register number are updated when instructions utilizing the given physical register number are retired. To reduce on-die real estate and power consumption, a single CAM entry is stores the physical register number and the other fields are stored in separate storage elements.

Abstract translation: 一种有效执行微架构检查点的系统和方法。 处理器内的寄存器重命名单元确定物理寄存器号码是否有资格具有重复的映射。 维护重复映射的信息存储在寄存器重复数组（RDA）中。 为了减少错误或异常恢复的处罚，处理器中的控制逻辑支持多个检查点。 RDA是具有状态检查点副本的多个数据结构之一。 RDA利用内容可寻址存储器（CAM）来存储物理寄存器编号。 对于给定的物理寄存器号码的当前状态和检查点副本的重复计数将在使用给定物理寄存器号码的指令退出时更新。 为了降低裸片上的不动产和功耗，单个CAM条目存储物理寄存器号，其他字段存储在单独的存储元件中。

公开(公告)号：US09223577B2

公开(公告)日：2015-12-29

申请号：US13627884

申请日：2012-09-26

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Gerard R. Williams, III ,  James B. Keller ,  Fang Liu ,  Shyam Sundar

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/3867

Abstract: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.

Abstract translation: 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。