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    Software only inter-compute unit redundant multithreading for GPUs
    13.
    发明授权
    Software only inter-compute unit redundant multithreading for GPUs 有权
    用于GPU的仅软件间计算单元冗余多线程

    公开(公告)号：US09274904B2

    公开(公告)日：2016-03-01

    申请号：US13920524

    申请日：2013-06-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander Lyashevsky ,  Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F9/46 ,  G06F11/00 ,  G06F11/20 ,  G06F9/52 ,  G06F11/16

    CPC classification number: G06F11/00 ,  G06F9/3851 ,  G06F9/52 ,  G06F11/1608 ,  G06F11/1633 ,  G06F11/1637 ,  G06F11/1654 ,  G06F11/1687 ,  G06F11/202 ,  G06F11/2038 ,  G06F11/2041 ,  G06F11/2048 ,  G06F2201/825 ,  G06F2201/83

    Abstract: A system, method and computer program product to execute a first and a second work-group, and compare the signature variables of the first work-group to the signature variables of the second work-group via a synchronization mechanism. The first and the second work-group are mapped to an identifier via software. This mapping ensures that the first and second work-groups execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-groups independently, the underlying computation of the first and second work-groups can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-groups are compared only at specified comparison points.

    Abstract translation: 一种用于执行第一和第二工作组的系统，方法和计算机程序产品，并且经由同步机制将第一工作组的签名变量与第二工作组的签名变量进行比较。 第一个和第二个工作组通过软件映射到一个标识符。 此映射确保第一个和第二个工作组对完全相同的代码执行完全相同的数据，而不会更改底层硬件。 通过独立地执行第一和第二工作组，可以验证第一和第二工作组的基础计算。 此外，由于第一和第二工作组的执行结果仅在指定的比较点进行比较，系统性能基本上不受影响。

    Signature-based store checking buffer
    14.
    发明授权
    Signature-based store checking buffer 有权
    基于签名的商店检查缓冲区

    公开(公告)号：US09047192B2

    公开(公告)日：2015-06-02

    申请号：US13724987

    申请日：2012-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vilas Sridharan ,  Sudhanva Gurumurthi

    IPC: G06F11/00 ,  G06F11/08 ,  G06F11/10 ,  G06F17/30 ,  G06F11/16

    CPC classification number: G06F11/08 ,  G06F11/1004 ,  G06F11/167 ,  G06F17/30743

    Abstract: A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free.

    Abstract translation: 提供了一种用于优化冗余输出验证的系统和方法。 基于硬件的商店指纹缓冲器从多个计算实例接收多个输出实例。 存储指纹缓冲区从包含在输出的多个实例中的内容生成签名。 当达到屏障时，商店指纹缓冲区使用签名来验证内容是否无错误。

    Signature-Based Store Checking Buffer
    15.
    发明申请
    Signature-Based Store Checking Buffer 有权
    基于签名的商店检查缓冲区

    公开(公告)号：US20140181594A1

    公开(公告)日：2014-06-26

    申请号：US13724987

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Vilas SRIDHARAN ,  Sudhanva Gurumurthi

    IPC: G06F11/08

    CPC classification number: G06F11/08 ,  G06F11/1004 ,  G06F11/167 ,  G06F17/30743

    Abstract: A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free.

    Abstract translation: 提供了一种用于优化冗余输出验证的系统和方法。 基于硬件的商店指纹缓冲器从多个计算实例接收多个输出实例。 存储指纹缓冲区从包含在输出的多个实例中的内容生成签名。 当达到屏障时，商店指纹缓冲区使用签名来验证内容是否无错误。

    PROCESSOR SUPPORT FOR SOFTWARE-LEVEL CONTAINMENT OF ROW HAMMER ATTACKS
    16.
    发明公开
    PROCESSOR SUPPORT FOR SOFTWARE-LEVEL CONTAINMENT OF ROW HAMMER ATTACKS 审中-公开

    公开(公告)号：US20230195889A1

    公开(公告)日：2023-06-22

    申请号：US17559520

    申请日：2021-12-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F21/55 ,  G11C11/406 ,  G06F21/79

    CPC classification number: G06F21/554 ,  G11C11/40618 ,  G11C11/40611 ,  G06F21/79

    Abstract: A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.

    Temperature-based adjustments for in-memory matrix multiplication
    18.
    发明授权
    Temperature-based adjustments for in-memory matrix multiplication 有权

    公开(公告)号：US11507641B2

    公开(公告)日：2022-11-22

    申请号：US16428903

    申请日：2019-05-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Majed Valad Beigi ,  Amin Farmahini-Farahani ,  Sudhanva Gurumurthi

    IPC: G06F17/16 ,  G01K3/14 ,  G01K3/10

    Abstract: Techniques for performing in-memory matrix multiplication, taking into account temperature variations in the memory, are disclosed. In one example, the matrix multiplication memory uses ohmic multiplication and current summing to perform the dot products involved in matrix multiplication. One downside to this analog form of multiplication is that temperature affects the accuracy of the results. Thus techniques are provided herein to compensate for the effects of temperature increases on the accuracy of in-memory matrix multiplications. According to the techniques, portions of input matrices are classified as effective or ineffective. Effective portions are mapped to low temperature regions of the in-memory matrix multiplier and ineffective portions are mapped to high temperature regions of the in-memory matrix multiplier. The matrix multiplication is then performed.

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