公开(公告)号：US11809874B2

公开(公告)日：2023-11-07

申请号：US17590722

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia ,  Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30058 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3885

Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.

公开(公告)号：US09684516B2

公开(公告)日：2017-06-20

申请号：US14842915

申请日：2015-09-02

Applicant: APPLE INC.

Inventor： Wei-Han Lien

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3012 ,  G06F9/30123

Abstract: A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry.

公开(公告)号：US20140380071A1

公开(公告)日：2014-12-25

申请号：US13924164

申请日：2013-06-21

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.

Abstract translation: 在一个实施例中，系统可以包括多个处理器和配置成在各个操作点之间切换处理器的自动功率状态控制器（APSC）。 操作点可以由编程到APSC中的数据描述，并且APSC可以包括可编程的寄存器，其具有从所描述的操作点中识别处理器的目标操作点的目标操作点请求。 描述操作点的数据还可以包括在操作点处可能同时活动的处理器的数量是否受限制的指示。 基于指示和有效处理器的数量，APSC可以以减小的操作点覆盖所请求的操作点。 在一些实施例中，数字功率估计器（DPE）可以监视处理器的操作，并且可以在检测到高功耗时调节处理器。

公开(公告)号：US20140317425A1

公开(公告)日：2014-10-23

申请号：US13864723

申请日：2013-04-17

Applicant: APPLE INC.

Inventor： Wei-Han Lien ,  Gerard R. Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R. Wen

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。

公开(公告)号：US20140244976A1

公开(公告)日：2014-08-28

申请号：US13774093

申请日：2013-02-22

Applicant: APPLE INC.

Inventor： Shyam Sundar ,  Ian D. Kountanis ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Wei-Han Lien ,  Ramesh B. Gunna

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844

Abstract: Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

Abstract translation: 用于在IT指令块内处理和预解码分支的各种技术。 指令被取出并缓存在指令高速缓存中，并且生成预解码位以指示IT指令的存在以及IT指令块的可能边界。 如果在IT指令块的可能边界内检测到无条件分支，则无条件分支被视为是条件分支。 无条件分支被发送到分支方向预测器，预测器产生无条件分支的分支方向预测。

公开(公告)号：US20140195789A1

公开(公告)日：2014-07-10

申请号：US13735694

申请日：2013-01-07

Applicant: APPLE INC.

Inventor： Sandeep Gupta ,  Shyam Sundar ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Conrado Blasco-Allue

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/30072 ,  G06F9/3806 ,  G06F9/3848

Abstract: A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries.

Abstract translation: 用于实现分支目标缓冲器的电路。 分支目标缓冲器可以包括存储多个条目的存储器。 每个条目可以包括标签值，目标值和预测精度值。 对应于间接分支指令的接收到的索引值可以用于选择多个条目中的一个条目，然后将接收的标签值与存储器中所选条目的标签值进行比较。 响应于接收到的标签与被比较的条目的标签值不匹配的确定，可以选择存储器中的条目。 所选择的条目可以根据多个条目的预测精度值分配给间接指令分支。

公开(公告)号：US11829763B2

公开(公告)日：2023-11-28

申请号：US16539684

申请日：2019-08-13

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Viney Gautam ,  Wei-Han Lien ,  Kulin N. Kothari ,  Mridul Agarwal

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  G06F12/0802

CPC classification number: G06F9/3455 ,  G06F9/30043 ,  G06F9/3861 ,  G06F9/5005 ,  G06F12/0802

Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

公开(公告)号：US11003233B2

公开(公告)日：2021-05-11

申请号：US16379231

申请日：2019-04-09

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/26 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/3287 ,  G06F9/50 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3215

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.

公开(公告)号：US20210049015A1

公开(公告)日：2021-02-18

申请号：US16539684

申请日：2019-08-13

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Viney Gautam ,  Wei-Han Lien ,  Kulin N. Kothari ,  Mridul Agarwal

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  G06F12/0802

Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

公开(公告)号：US09411360B2

公开(公告)日：2016-08-09

申请号：US14153296

申请日：2014-01-13

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Wei-Han Lien ,  Shih-Chieh R. Wen

IPC: G06F1/08 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.

Abstract translation: 一种用于管理时钟信号频率变化的系统，包括被配置为输出时钟信号的时钟发生器，耦合到时钟发生器的输出的时钟分配器，被配置为选择时钟信号的频率的处理器，以及 一个时钟管理电路。 时钟管理电路可以被配置为设置时钟发生器以将时钟信号调整到所选择的频率。 时钟管理电路还可以被配置为响应于以所选频率稳定的时钟信号的确定，在多个步骤中调整时钟分频器的除数值。 可以在多个步骤中的每个步骤期间选择新的除数值，并且每个步骤可以在给定时间段之后发生。