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    Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage
    11.
    发明授权
    Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage 有权
    通过分割单个目标操作阶段并合并操作码执行操作阶段来处理多目标指令

    公开(公告)号：US09223577B2

    公开(公告)日：2015-12-29

    申请号：US13627884

    申请日：2012-09-26

    Applicant: Apple Inc.

    Inventor： John H. Mylius ,  Gerard R. Williams, III ,  James B. Keller ,  Fang Liu ,  Shyam Sundar

    IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3017 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/3867

    Abstract: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.

    Abstract translation: 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。

    Trust Zone Support in System on a Chip Having Security Enclave Processor
    12.
    发明申请
    Trust Zone Support in System on a Chip Having Security Enclave Processor 有权
    在具有安全处理器的芯片上的系统中的信任区域支持

    公开(公告)号：US20140089617A1

    公开(公告)日：2014-03-27

    申请号：US13626546

    申请日：2012-09-25

    Applicant: APPLE INC.

    Inventor： R. Stephen Polzin ,  James B. Keller ,  Gerard R. Williams, III

    IPC: G06F12/14

    CPC classification number: G06F12/14 ,  G06F12/1441 ,  G06F21/575 ,  G06F21/74

    Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

    Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

    Combined transparent/non-transparent cache
    13.
    发明授权
    Combined transparent/non-transparent cache 有权

    公开(公告)号：US10776022B2

    公开(公告)日：2020-09-15

    申请号：US16266320

    申请日：2019-02-04

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/123 ,  G06F12/0831 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/0846 ,  G06F12/0853

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

    Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch
    15.
    发明申请
    Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch 审中-公开
    广泛问题的分支预测器，任意对齐获取

    公开(公告)号：US20160048395A1

    公开(公告)日：2016-02-18

    申请号：US14923947

    申请日：2015-10-27

    Applicant: Apple Inc.

    Inventor： Ian D. Kountanis ,  Gerard R. Williams, III ,  James B. Keller

    IPC: G06F9/38

    CPC classification number: G06F9/3842 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/38 ,  G06F9/3844 ,  G06F9/3848

    Abstract: In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch.

    Abstract translation: 在一个实施例中，处理器可以被配置为从指令高速缓存（“取出组”）获取N个指令字节，即使获取组跨越高速缓存行边界。 分支预测器可以被配置为在获取组中产生多达M个分支的分支预测，其中M是可以包括在获取组中的最大分支数。 在一个实施例中，分支方向预测器可以响应于错误预测而被更新，并且还响应于在预测之间的转换阈值内的分支预测。 为了避免查找以确定是否要执行阈值更新，分支预测器可以在预测期间检测阈值更新，并且可以用分支发送指示。

    Combined transparent/non-transparent cache
    16.
    发明授权
    Combined transparent/non-transparent cache 有权
    组合透明/不透明缓存

    公开(公告)号：US08977818B2

    公开(公告)日：2015-03-10

    申请号：US14032405

    申请日：2013-09-20

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F12/00 ,  G06F12/12 ,  G06F12/08

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

    Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。

    Multi-Destination Instruction Handling
    17.
    发明申请
    Multi-Destination Instruction Handling 有权
    多目的地指令处理

    公开(公告)号：US20140089638A1

    公开(公告)日：2014-03-27

    申请号：US13627884

    申请日：2012-09-26

    Applicant: APPLE INC.

    Inventor： John H. Mylius ,  Gerard R. Williams III ,  James B. Keller ,  Fang Liu ,  Shyam Sundar

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3017 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/3867

    Abstract: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.

    Abstract translation: 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。

    Combined Transparent/Non-Transparent Cache
    18.
    发明申请
    Combined Transparent/Non-Transparent Cache 有权
    组合透明/不透明缓存

    公开(公告)号：US20140025900A1

    公开(公告)日：2014-01-23

    申请号：US14032405

    申请日：2013-09-20

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F12/12

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

    Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。

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