-
公开(公告)号：US10198726B2
公开(公告)日：2019-02-05
申请号：US14500927
申请日：2014-09-29
Applicant: Apple Inc.
Inventor： Cyril de la Cropte de Chanterac , Joseph Hakim , Leland W. Lew , Hue Duc Tran
Abstract: This application relates to systems, methods, and apparatus for using a computing device to perform payment transactions while the computing device is operating in a low power wallet mode during a low battery state of the computing device. During a low power wallet mode, various subsystems are prevented from receiving current from a battery of the computing device, while a near field communication (NFC) system of the computing device is provided with an operating current for detecting target systems. A target system and the NFC system can communicate during the low power wallet mode of the computing device, thereby allowing a user of the computing device to conduct payment transactions when the computing device is in a low power wallet mode. Such payment transactions can be useful if the user is ever stranded without enough power to fully operate the computing device and needs to pay for transportation.
-
12.发明申请公开(公告)号：US20180349186A1
公开(公告)日：2018-12-06
申请号：US15870764
申请日：2018-01-12
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol
Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
-
公开(公告)号：US09980232B2
公开(公告)日：2018-05-22
申请号：US14726503
申请日：2015-05-30
Applicant: APPLE INC.
Inventor： Matthew L. Semersky , David A. Hardell , Cyril de la Cropte de Chanterac , Yehonantan Perez
IPC: H04W52/02
CPC classification number: H04W52/0277 , H04W52/0229 , H04W52/0238 , H04W52/0274 , Y02D70/00 , Y02D70/142 , Y02D70/144 , Y02D70/166 , Y02D70/26
Abstract: Circuits, methods, and apparatus that react to brownout or near brownout conditions and mitigate complications that may result. Examples may turn off one or more circuits, such as a Wi-Fi transceiver when a brownout condition is reached or neared. Other examples may provide circuits, methods, and apparatus that proactively avoid brownout conditions. These examples may detect that a brownout condition may occur and take steps, such as Wi-Fi traffic shaping, to avoid them. Still further examples may react to brownout or near brownout conditions one or more times, then preemptively act to avoid further brownout conditions.
-
公开(公告)号：US20170083069A1
公开(公告)日：2017-03-23
申请号：US14858035
申请日：2015-09-18
Applicant: Apple Inc.
Inventor： Joseph T. DiBene, II , Jafar Savoj , Inder M. Sodhi , Cyril de la Cropte de Chanterac , Sotirios Zogopoulos
IPC: G06F1/28 , G01R19/25 , G06F1/26 , G01R19/255
CPC classification number: G06F1/28 , G01R19/2506 , G01R19/255 , G06F1/26 , G06F1/263
Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.
-
公开(公告)号：US20160077136A1
公开(公告)日：2016-03-17
申请号：US14487472
申请日：2014-09-16
Applicant: Apple Inc.
Inventor： Daniel U. Becker , Cyril de la Cropte de Chanterac
CPC classification number: G06F1/3203 , G06F1/3212 , G06F1/329 , G06F9/5094 , Y02D10/174 , Y02D10/24
Abstract: Embodiments of a computing system that may monitor energy usage are disclosed. The embodiments may provide a low overhead method for determining energy usage of a given application or process. Circuitry is configured to determine a respective energy for each of the plurality of operations and sum each respective energy for at least some of the plurality of operations to generate a normalized total. The circuitry may be further configured to scale the normalized total to generate an energy value, and store the energy value in a register. System software may then read the energy value from the register and determine an energy usage for at least one application dependent upon the energy value.
Abstract translation: 公开了可以监测能量使用的计算系统的实施例。 这些实施例可以提供用于确定给定应用或过程的能量使用的低开销方法。 电路被配置为为多个操作中的每一个确定相应的能量，并对多个操作中的至少一些操作求和各个能量以产生归一化总计。 电路还可以被配置为缩放归一化总计以产生能量值，并将能量值存储在寄存器中。 然后，系统软件可以从寄存器读取能量值，并根据能量值确定至少一个应用的能量使用。
-
Patent Agency Ranking
16.发明申请公开(公告)号：US20160054773A1
公开(公告)日：2016-02-25
申请号：US14466205
申请日：2014-08-22
Applicant: Apple Inc.
Inventor： Manu Gulati , Parin Patel , Keith Cox , Derek Iwamoto , Cyril de la Cropte de Chanterac , Christopher J. Young
IPC: G06F1/32
CPC classification number: G06F1/3203 , G06F1/3296 , Y02D10/172
Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.
Abstract translation: 公开了一种用于提供用于功率控制功能的遥测的方法和装置。 一种系统包括具有第一电源管理电路的集成电路（IC）。 IC还包括多个不同功率域内的多个功能电路块。 第二电源管理电路在IC外部实现并且包括多个电压调节器。 每个电源域被耦合以从一个电压调节器接收电力。 在操作期间，第一电源管理电路可以发送请求改变提供给IC的一个或多个电压的命令。 第二电力管理电路可以通过执行所请求的电压变化来响应，并且还可以向第一电力管理电路提供遥测数据。 第二电力管理电路还可以响应于从第一电力管理电路接收无操作命令来提供遥测数据。
-
公开(公告)号：US20140337649A1
公开(公告)日：2014-11-13
申请号：US13890306
申请日：2013-05-09
Applicant: APPLE INC.
Inventor： Sukalpa Biswas , Shinye Shiu , Cyril de la Cropte de Chanterac , Manu Gulati , Pulkit Desai , Rong Zhang Hu
IPC: G06F1/32
CPC classification number: G06F1/3275 , G06F1/3218 , G06F1/3287 , G06F3/14 , G06F12/0873 , G06F2212/455 , G09G5/001 , G09G5/393 , G09G5/395 , G09G2330/02 , G09G2330/021 , G09G2360/121
Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。
-
公开(公告)号：US20240146356A1
公开(公告)日：2024-05-02
申请号：US18390929
申请日：2023-12-20
Applicant: Apple Inc.
Inventor： Kartik R. Venkatraman , Shardul S. Mangade , Alessandro Pelosi , Cyril de la Cropte de Chanterac
Abstract: An electronic device may have a power system. The power system may receive power such as wireless power or wired power and may use a portion of the received power to charge a battery. Power consumption by control circuitry in the device can be adjusted by deactivating or activating processor cores in the control circuitry and by selectively starting or stopping software activities. By selectively reducing power consumption by circuitry in the electronic device other than battery charging circuitry in the power system that is charging the battery, additional power may be made available to charge the battery and/or battery capacity can be extended. The electronic device may reduce non-battery-charging activities in the device in response to information gathered with sensors such as motion and temperature information, information from the power system, information on device location, information on software settings, and other information.
-
公开(公告)号：US20240053410A1
公开(公告)日：2024-02-15
申请号：US17819771
申请日：2022-08-15
Applicant: Apple Inc.
Inventor： Cyril de la Cropte de Chanterac , Lawrence A. Cayton , Brian C. Beer , Shardul S. Mangade , Farman A. Syed , Andrea R. Romano
IPC: G01R31/396 , G01R31/367
CPC classification number: G01R31/396 , G01R31/367
Abstract: An electronic device can include a processor programmed to detect connection of an external power source to the electronic device, determine an estimated disconnection time at which the external power source is expected to be disconnected from the electronic device, analyze power grid data corresponding to the external power source to identify one or more desired background processing intervals and one or more undesired background processing intervals prior to the estimated disconnection time, and perform background processing during the identified one or more desired battery charging intervals and inhibit background processing during the one or more undesired battery charging intervals. The processor can be programmed to determine an estimated disconnection time using a machine learning model. The processor can be programmed to inhibit background processing by reducing the amount of background processing during certain undesired background processing intervals or by preventing background processing during certain undesired background processing intervals.
-
20.发明授权公开(公告)号：US11080095B2
公开(公告)日：2021-08-03
申请号：US15870766
申请日：2018-01-12
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol
IPC: G06F9/46 , G06F9/50 , G06F9/48 , G06F1/3234 , G06F1/329 , G06F1/3296 , G06F9/38 , G06F9/26 , G06F9/54 , G06F1/20 , G06F1/324 , G06F1/3206 , G06F9/30
Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
-
-
-
-
-
-
-
-
-
Search Results
54
records
(took 0.034 seconds)
