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    POWER MANAGEMENT OF DISPLAY DATA DURING AN IDLE SCREEN
    11.
    发明公开
    POWER MANAGEMENT OF DISPLAY DATA DURING AN IDLE SCREEN 审中-公开

    公开(公告)号：US20240331659A1

    公开(公告)日：2024-10-03

    申请号：US18128797

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Dennis Kin-Wah Au ,  Oswin Hall ,  Ashish Jain

    IPC: G09G5/36

    CPC classification number: G09G5/363 ,  G09G2330/021 ,  G09G2360/123

    Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple functional blocks. When control circuitry detects a low-performance mode, commands are sent to the multiple functional blocks specifying storing data of the given type in a contiguous manner in one or more of the caches of the multiple functional blocks and the memories connected to the multiple functional blocks. Following, the control circuitry transitions the memories to a sleep state and transitions all but one of the functional blocks to the sleep state. The functional blocks rotate amongst themselves with a single functional block being in the active state and servicing requests based on which data of the given type is targeted by the requests.

    Droop detection and control of digital frequency-locked loop
    14.
    发明授权
    Droop detection and control of digital frequency-locked loop 有权

    公开(公告)号：US12278638B2

    公开(公告)日：2025-04-15

    申请号：US18525071

    申请日：2023-11-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Kaushik Mazumdar ,  Ashish Jain ,  Joyce Cheuk Wai Wong ,  Mikhail Rodionov

    IPC: H03L7/08 ,  G01R19/165

    Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.

    Frequency/state based power management thresholds
    15.
    发明授权
    Frequency/state based power management thresholds 有权

    公开(公告)号：US12164353B2

    公开(公告)日：2024-12-10

    申请号：US17936740

    申请日：2022-09-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Shang Yang

    IPC: G06F1/3206

    Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI
    16.
    发明公开
    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI 审中-公开

    公开(公告)号：US20240334340A1

    公开(公告)日：2024-10-03

    申请号：US18128805

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Paul Blinzer ,  Chirag Nitinkumar Dhruv ,  Ranjeet Kumar ,  Gia Tung Phan ,  Ashish Jain

    IPC: H04W52/02

    CPC classification number: H04W52/029 ,  H04W52/0274

    Abstract: An apparatus and method for efficiently performing power management for increasing reliable wireless signal transfer performed by mobile computing devices. In various implementations, a computing system includes a network interface and multiple components for processing tasks. The network interface sends, to at least a given component of the multiple components, an indication specifying the corresponding operating frequency ranges used by one or more radio modules used for wireless communication with an access point. The given component determines whether an operating clock frequency of the given component overlaps any of the received operating frequency ranges and associated harmonic frequencies. If so, then the given component changes the operating clock frequency to a frequency that does not overlap any of the received operating frequency ranges and associated harmonic frequencies.

    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT
    17.
    发明公开
    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240319781A1

    公开(公告)日：2024-09-26

    申请号：US18189993

    申请日：2023-03-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Randall Brown ,  Ashish Jain

    IPC: G06F1/3234 ,  G06F1/3228 ,  G06F1/3287

    CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287

    Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.

    PLATFORM EFFICIENCY TRACKER
    19.
    发明公开
    PLATFORM EFFICIENCY TRACKER 审中-公开

    公开(公告)号：US20240004448A1

    公开(公告)日：2024-01-04

    申请号：US17853759

    申请日：2022-06-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Eric D. Meyer ,  Austin Hung ,  Tianshu Liu

    IPC: G06F1/28 ,  G06F11/30

    CPC classification number: G06F1/28 ,  G06F11/3062

    Abstract: Systems, apparatuses, and methods for dynamically estimating power losses in a computing system. A system management circuit tracks a state of a computing system and dynamically estimates power losses in the computing system based in part on the state. Based on the estimated power losses, power consumption of the computing system is estimated. In response to detecting reduced power losses in at least a portion of the computing system, the system management circuit is configured to increase a power-performance state of one or more circuits of the computing system while remaining within a power allocation limit of the computing system.

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