公开(公告)号：US20160124873A1

公开(公告)日：2016-05-05

申请号：US14891523

申请日：2013-05-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

IPC: G06F13/16 ,  G06F1/32 ,  G11C7/10

Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

Abstract translation: 集成电路装置包括可耦合到存储器的存储器控​​制器。 所述存储器控制器基于所述区域特有的存储器定时参数来调度对所述存储器的区域的存储器访问。 一种方法包括在存储器设备处接收存储器访问请求。 该方法还包括从存储器设备的定时数据存储器访问表示存储器定时参数的特定于存储器访问请求所针对的存储器单元电路区域的数据。 该方法还包括在存储器控制器的基础上调度存储器访问请求。

公开(公告)号：US11474703B2

公开(公告)日：2022-10-18

申请号：US17199949

申请日：2021-03-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G06F1/3203 ,  G11C7/10

Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

公开(公告)号：US09767043B2

公开(公告)日：2017-09-19

申请号：US14229420

申请日：2014-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

IPC: G06F12/126 ,  G06F3/06 ,  G06F12/00 ,  G06F12/0871 ,  G06F12/0808 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/126 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0628 ,  G06F3/0653 ,  G06F3/0673 ,  G06F3/0674 ,  G06F3/0676 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0871 ,  G06F12/12 ,  G06F12/121

Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.

公开(公告)号：US09639359B2

公开(公告)日：2017-05-02

申请号：US13976905

申请日：2013-05-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Yuan Xie ,  Junli Gu

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/30083 ,  G06F8/4432 ,  G06F9/30087 ,  G06F9/30149 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D10/41

Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.