公开(公告)号：US20200257623A1

公开(公告)日：2020-08-13

申请号：US16274146

申请日：2019-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin ,  Yasuko Eckert ,  Matthew R. Poremba ,  Steven E. Raasch ,  Doug Hunt

IPC: G06F12/0802

Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.

公开(公告)号：US10389251B2

公开(公告)日：2019-08-20

申请号：US16130136

申请日：2018-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Yasuko Eckert ,  Xudong An ,  Muhammad Shoaib Bin Altaf ,  Jieming Yin

IPC: H02M3/158 ,  G05F1/56 ,  G05F1/46 ,  G05F1/575 ,  H02M1/00

Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.

公开(公告)号：US12079634B2

公开(公告)日：2024-09-03

申请号：US16794124

申请日：2020-02-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur Kayiran ,  Jieming Yin ,  Yasuko Eckert

IPC: G06F9/38 ,  G06F8/41 ,  G06N10/00

CPC classification number: G06F9/3887 ,  G06F8/41 ,  G06N10/00

Abstract: A technique for processing qubits in a quantum computing device is provided. The technique includes determining that, in a first cycle, a first quantum processing region is to perform a first quantum operation that does not use a qubit that is stored in the first quantum processing region, identifying a second quantum processing region that is to perform a second quantum operation at a second cycle that is later than the first cycle, wherein the second quantum operation uses the qubit, determining that between the first cycle and the second cycle, no quantum operations are performed in the second quantum processing region, and moving the qubit from the first quantum processing region to the second quantum processing region.

公开(公告)号：US11150899B2

公开(公告)日：2021-10-19

申请号：US15948795

申请日：2018-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony T. Gutierrez ,  Sergey Blagodurov ,  Scott A. Moe ,  Xianwei Zhang ,  Jieming Yin ,  Matthew D. Sinclair

IPC: G06F9/30 ,  G06F8/71 ,  G06N3/063 ,  G06N3/08

Abstract: An electronic device includes a controller functional block and a computational functional block. During operation, while the computational functional block executes a test portion of a workload at at least one precision level, the controller functional block monitors a behavior of the computational functional block. Based on the behavior of the computational functional block while executing the test portion of the workload at the at least one precision level, the controller functional block selects a given precision level from among a set of two or more precision levels at which the computational functional block is to execute a remaining portion of the workload. The controller functional block then configures the computational block to execute the remaining portion of the workload at the given precision level.

公开(公告)号：US20210255871A1

公开(公告)日：2021-08-19

申请号：US16794124

申请日：2020-02-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur Kayiran ,  Jieming Yin ,  Yasuko Eckert

IPC: G06F9/38 ,  G06N10/00 ,  G06F8/41

Abstract: A technique for processing qubits in a quantum computing device is provided. The technique includes determining that, in a first cycle, a first quantum processing region is to perform a first quantum operation that does not use a qubit that is stored in the first quantum processing region, identifying a second quantum processing region that is to perform a second quantum operation at a second cycle that is later than the first cycle, wherein the second quantum operation uses the qubit, determining that between the first cycle and the second cycle, no quantum operations are performed in the second quantum processing region, and moving the qubit from the first quantum processing region to the second quantum processing region.

公开(公告)号：US10719441B1

公开(公告)日：2020-07-21

申请号：US16274146

申请日：2019-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin ,  Yasuko Eckert ,  Matthew R. Poremba ,  Steven E. Raasch ,  Doug Hunt

IPC: G06F12/0802

Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.

公开(公告)号：US10097091B1

公开(公告)日：2018-10-09

申请号：US15793951

申请日：2017-10-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Yasuko Eckert ,  Xudong An ,  Muhammad Shoaib Bin Altaf ,  Jieming Yin

IPC: G05F1/00 ,  H02M3/158 ,  G05F1/575 ,  G05F1/46 ,  G05F1/56 ,  H02M1/00

Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.