公开(公告)号：US07830280B2

公开(公告)日：2010-11-09

申请号：US12453109

申请日：2009-04-29

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03M5/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于传输的数据，对接收到的数据内的比特数进行加扰，根据给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US20100144162A1

公开(公告)日：2010-06-10

申请号：US12553759

申请日：2009-09-03

申请人： Woo Jin Lee ,  Akira Shimizu

发明人： Woo Jin Lee ,  Akira Shimizu

IPC分类号： H01L21/314

CPC分类号： H01L21/3185 ,  C23C16/345 ,  C23C16/45523 ,  C23C16/5096 ,  H01L21/31111

摘要： A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

摘要翻译： 通过等离子体增强化学气相沉积（PECVD）在半导体衬底上形成具有Si-N键的共形电介质膜的方法包括：将含氮和氢的反应气体和添加气体引入反应空间内， 底物放置; 向反应空间施加RF功率; 并将含氢的硅前体以脉冲方式引入到等离子体被激发的反应空间中，从而在衬底上形成具有Si-N键的保形电介质膜。

公开(公告)号：US20100124621A1

公开(公告)日：2010-05-20

申请号：US12618355

申请日：2009-11-13

申请人： Akiko Kobayashi ,  Akira Shimizu ,  Nobuyoshi Kobayashi ,  Woo-Jin Lee

发明人： Akiko Kobayashi ,  Akira Shimizu ,  Nobuyoshi Kobayashi ,  Woo-Jin Lee

IPC分类号： C23C16/48

CPC分类号： C23C16/402 ,  C23C16/325 ,  C23C16/345 ,  C23C16/45542 ,  C23C16/45553 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228

摘要： A method of forming an insulation film by alternating multiple times, respectively, a process of adsorbing a precursor onto a substrate and a process of treating the adsorbed surface using reactant gas and a plasma, wherein a plasma is applied in the process of supplying the precursor.

摘要翻译： 一种通过交替多次交替形成绝缘膜的方法，将前体吸附到基底上的方法和使用反应气体和等离子体处理吸附表面的方法，其中在提供前体的过程中施加等离子体 。

公开(公告)号：US07515790B2

公开(公告)日：2009-04-07

申请号：US11974635

申请日：2007-10-15

申请人： Choon Gi Choi ,  Young Tak Han ,  Jin Tae Kim ,  Woo Jin Lee

发明人： Choon Gi Choi ,  Young Tak Han ,  Jin Tae Kim ,  Woo Jin Lee

IPC分类号： G02B6/10 ,  G02B6/34 ,  G02B5/04

CPC分类号： G02B6/1225 ,  B82Y20/00 ,  G02B6/1221

摘要： Provided are a two-dimensional planar photonic crystal superprism device and a method of manufacturing the same, in which a manufacturing process is simplified using a nanoimprint lithography technique, and thus price-reduction and mass production are facilitated. The two-dimensional planar photonic crystal superprism device includes: a single-mode input waveguide comprising a straight waveguide having a taper structure and a bending waveguide; a superprism formed on an output end side of the single-mode input waveguide and comprising a slab and a photonic crystal superprism; and a single-mode output waveguide comprising a straight waveguide having a taper structure and a bending waveguide, and formed adjacent to the photonic crystal superprism. Using the two-dimensional planar photonic crystal superprism device, it is possible to facilitate manufacturing of nano-photonic integrated circuits, photonic crystal integrated circuits and nano-photonic systems. In addition, a wavelength-selectable photonic crystal superprism device using high dispersion of photonic crystal, which is several hundred times the dispersion of conventional glass prism, can be manufactured using thermal/hot and ultraviolet nanoimprint lithography techniques corresponding to nano-manufacturing technology.

摘要翻译： 提供了一种二维平面光子晶体超控装置及其制造方法，其中使用纳米压印光刻技术简化了制造工艺，因此有利于价格降低和批量生产。 二维平面光子晶体超导装置包括：单模输入波导，包括具有锥形结构的直波导管和弯曲波导; 形成在单模输入波导的输出端侧并且包括平板和光子晶体超控的超实例; 以及单模输出波导，其包括具有锥形结构的直波导管和弯曲波导，并且与光子晶体超立体相邻地形成。 使用二维平面光子晶体超微元器件，可以促进纳米光子集成电路，光子晶体集成电路和纳米光子系统的制造。 此外，使用对应于纳米制造技术的热/热和紫外线纳米压印光刻技术可以制造使用高分散度的光子晶体的波长可选择的光子晶体超大容量器件，其是常规玻璃棱镜的百分之几。

公开(公告)号：US07499341B2

公开(公告)日：2009-03-03

申请号：US11601027

申请日：2006-11-17

申请人： Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

发明人： Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

IPC分类号： G11C7/10

CPC分类号： G11C29/48 ,  G11C7/1051 ,  G11C7/1069 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14

摘要： A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.

摘要翻译： 描述半导体存储器件和扩展有效输出数据窗口的方法。 半导体存储器件包括存储单元阵列和输出电路。 存储单元阵列产生具有多个位的读取数据。 输出电路响应于正常模式下的时钟信号顺序地输出读取的数据。 另一方面，输出电路通过在读取数据的比特之间锁存待测试的比特来选择性地输出读取的数据的比特，并且响应于多个读取数据，通过电连接在读取的数据的比特之间的不被测试的比特 在测试模式下切换控制信号。 因此，可以扩展输出数据的有效数据窗口。

公开(公告)号：US07420387B2

公开(公告)日：2008-09-02

申请号：US11402123

申请日：2006-04-11

申请人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

发明人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

摘要翻译： 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。

公开(公告)号：US07394720B2

公开(公告)日：2008-07-01

申请号：US11560746

申请日：2006-11-16

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

IPC分类号： G11C8/00

CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US07391238B2

公开(公告)日：2008-06-24

申请号：US11429296

申请日：2006-05-05

申请人： Hyun-Jin Kim ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： G06F13/4072 ,  H04L25/0278 ,  H04L25/028

摘要： A semiconductor memory device includes a primary output driver which outputs a data signal through an output terminal; a secondary output driver which is connected to the output terminal and performs a pre-emphasis operation; and a pre-emphasis signal generator which outputs a pre-emphasis signal to enable the secondary output driver The pre-emphasis signal generator includes a auto pulse generator which generates an auto pulse in response to a transition of a control signal; a delay circuit which receives the auto pulse output from the auto pulse generator, delays the auto pulse by a predetermined period, and outputs a pre-emphasis signal; and a delay control unit which applies a delay control signal to the delay circuit and controls a delay amount of the delay circuit.

摘要翻译： 半导体存储器件包括通过输出端输出数据信号的初级输出驱动器; 二次输出驱动器，其连接到输出端子并执行预加重操作; 以及预加重信号发生器，其输出预加重信号以使得辅助输出驱动器。预加重信号发生器包括自动脉冲发生器，其响应于控制信号的转变而产生自动脉冲; 接收从自动脉冲发生器输出的自动脉冲的延迟电路将自动脉冲延迟预定周期，并输出预加重信号; 以及延迟控制单元，其向延迟电路施加延迟控制信号并控制延迟电路的延迟量。

公开(公告)号：US20080052571A1

公开(公告)日：2008-02-28

申请号：US11892846

申请日：2007-08-28

申请人： Woo-Jin LEE ,  Seok-Won HWANG

发明人： Woo-Jin LEE ,  Seok-Won HWANG

IPC分类号： G11C29/08 ,  G11C29/00

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/025

摘要： Example embodiments relate to a memory test system having a semiconductor memory device, a coupling circuit and a tester. The semiconductor memory device may include a plurality of first output nodes and a plurality of second output nodes. The first output nodes may be connected to respective first on-die termination circuits that may not be tested, and the second output nodes may be connected to second on-die termination circuits that may be tested. The semiconductor memory device may be configured to generate test signals of the second on-die termination circuits and to provide the test signals to the second output nodes. The coupling circuit may be configured to connect the first output nodes and the second output nodes to communication channels, respectively. The tester may be configured to test a logic state of the test signals of the communication channels.

摘要翻译： 示例实施例涉及具有半导体存储器件，耦合电路和测试器的存储器测试系统。 半导体存储器件可以包括多个第一输出节点和多个第二输出节点。 第一输出节点可以连接到可能不被测试的相应的第一片上终端电路，并且第二输出节点可以连接到可以被测试的第二片上终端电路。 半导体存储器件可以被配置为产生第二片上终端电路的测试信号，并将测试信号提供给第二输出节点。 耦合电路可以被配置为分别将第一输出节点和第二输出节点连接到通信信道。 测试器可以被配置为测试通信信道的测试信号的逻辑状态。

公开(公告)号：US07205799B2

公开(公告)日：2007-04-17

申请号：US11225915

申请日：2005-09-13

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

IPC分类号： H03K3/00

CPC分类号： H03F3/45

摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

摘要翻译： 我们描述具有稳定的工作点和相关方法的输入缓冲器。 输入缓冲器可以包括第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。 响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。 第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。 第二差分放大单元可以响应于参考电压和输入电压信号而工作。 第一工作点可以相对高于第二工作点。