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57 条记录 (耗时 0.017 秒)

    METHOD OF FABRICATING A FLASH MEMORY DEVICE
    11.
    发明申请
    METHOD OF FABRICATING A FLASH MEMORY DEVICE 失效
    制造闪速存储器件的方法

    公开(公告)号：US20080268594A1

    公开(公告)日：2008-10-30

    申请号：US11856700

    申请日：2007-09-17

    申请人： Soo Jin Kim

    发明人： Soo Jin Kim

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： In a method of fabricating a flash memory device, a lower capping conductive layer of a peri region is patterned. A step formed between a cell gate and a gate for a peri region transistor is decreased by controlling a target etch thickness of a hard mask. Thus, an impurity does not infiltrate into the bottom of the gate for the peri region transistor through a lost portion of a SAC nitride layer. Accordingly, a hump phenomenon of the transistor formed in the peri region can be improved. Furthermore, a leakage current characteristic of the transistor formed in the peri region can be improved.

    摘要翻译： 在制造闪速存储器件的方法中，对围绕区域的下盖导电层进行图案化。 通过控制硬掩模的目标蚀刻厚度，减小了用于周边晶体管的单元栅极和栅极之间形成的台阶。 因此，通过SAC氮化物层的失去部分，杂质不会渗入到围绕晶体管的栅极的底部。 因此，能够提高在周边区域形成的晶体管的隆起现象。 此外，能够提高形成在周边区域的晶体管的漏电流特性。

    METHOD OF FORMING A GATE OF A SEMICONDUCTOR DEVICE
    12.
    发明申请
    METHOD OF FORMING A GATE OF A SEMICONDUCTOR DEVICE 有权
    形成半导体器件栅极的方法

    公开(公告)号：US20080160747A1

    公开(公告)日：2008-07-03

    申请号：US11761281

    申请日：2007-06-11

    申请人： Soo Jin Kim

    发明人： Soo Jin Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28247 ,  H01L21/28273 ,  H01L27/11521

    摘要： A method of forming a gate of a semiconductor device includes providing a semiconductor substrate over which a first conductive layer, a dielectric layer and a second conductive layer are formed. The second conductive layer is patterned to expose a part of the dielectric layer. A first protection layer is formed on sidewalls of the second conductive layer. A first etch process is performed to remove the exposed dielectric layer and to expose a part of the first conductive layer. A second protection layer is formed on sidewalls of the second conductive layer. A second etch process is performed to remove the exposed first conductive layer.

    摘要翻译： 形成半导体器件的栅极的方法包括提供半导体衬底，在其上形成第一导电层，电介质层和第二导电层。 图案化第二导电层以暴露电介质层的一部分。 第一保护层形成在第二导电层的侧壁上。 执行第一蚀刻工艺以去除暴露的介电层并暴露第一导电层的一部分。 第二保护层形成在第二导电层的侧壁上。 执行第二蚀刻工艺以去除暴露的第一导电层。

    Thin film transistor substrate and method for fabricating the same
    13.
    发明申请
    Thin film transistor substrate and method for fabricating the same 失效
    薄膜晶体管基板及其制造方法

    公开(公告)号：US20070018161A1

    公开(公告)日：2007-01-25

    申请号：US11433733

    申请日：2006-05-12

    申请人： Keun-kyu Song ,  Yong-uk Lee ,  Mun-pyo Hong ,  Tae-young Choi ,  Joon-hak Oh ,  Bo-sung Kim ,  Soo-jin Kim ,  Young-min Kim

    发明人： Keun-kyu Song ,  Yong-uk Lee ,  Mun-pyo Hong ,  Tae-young Choi ,  Joon-hak Oh ,  Bo-sung Kim ,  Soo-jin Kim ,  Young-min Kim

    IPC分类号： H01L29/04 ,  H01L21/84

    CPC分类号： H01L51/0533 ,  H01L51/107

    摘要： A thin film transistor substrate includes an insulating substrate, a gate electrode formed on the insulating substrate, a first gate insulating film formed on the gate electrode and having an opening for exposing at least part of the gate electrode, a second gate insulating film covering the gate electrode exposed by the opening and having a larger dielectric constant than the first gate insulating film, a source electrode and a drain electrode disposed apart from each other in a central area of the second gate insulating film and defining a channel region there between, and an organic semiconductor layer formed in the channel region. A method for forming the TFT substrate is also provided. Thus, the present invention provides a TFT substrate in which a characteristic of a TFT is improved.

    摘要翻译： 薄膜晶体管基板包括绝缘基板，形成在绝缘基板上的栅极电极，形成在栅电极上并具有用于暴露栅电极的至少一部分的开口的第一栅极绝缘膜，覆盖 栅电极由开口暴露并且具有比第一栅极绝缘膜更大的介电常数，在第二栅极绝缘膜的中心区域彼此分开设置的源电极和漏电极，并在其间限定沟道区域， 形成在沟道区域中的有机半导体层。 还提供了一种用于形成TFT基板的方法。 因此，本发明提供了TFT的特性提高的TFT基板。

    Gel polymer electrolyte and electrochemical device comprising the same
    15.
    发明授权
    Gel polymer electrolyte and electrochemical device comprising the same 有权
    凝胶聚合物电解质和包含其的电化学装置

    公开(公告)号：US08318361B2

    公开(公告)日：2012-11-27

    申请号：US12310771

    申请日：2007-09-07

    申请人： Sung-Hoon Yu ,  Jeong-Ju Cho ,  Soo-Jin Kim ,  Soo-Hyun Ha

    发明人： Sung-Hoon Yu ,  Jeong-Ju Cho ,  Soo-Jin Kim ,  Soo-Hyun Ha

    IPC分类号： H01M6/14

    CPC分类号： H01M10/0565

    摘要： Disclosed is a composition for a gel polymer electrolyte, the composition comprising: (i) a cyclic compound as a first crosslinking agent, the cyclic compound containing a cyclic group at the center thereof and having at least three double bonds at the end thereof; (ii) a linear or branched compound as a second crosslinking agent, the linear or branched compound containing an oxyalkylene group at the center thereof and having at least two (meth)acryl groups at the end thereof; (iii) an electrolyte solvent; (iv) an electrolyte salt; and (v) a polymerization initiator. Also, disclosed are a gel polymer electrolyte formed by polymerizing the composition for a gel polymer electrolyte, and an electrochemical device comprising the gel polymer electrolyte.

    摘要翻译： 公开了一种用于凝胶聚合物电解质的组合物，该组合物包含：（i）作为第一交联剂的环状化合物，其中心含有环状基团的环状化合物，末端具有至少三个双键; （ii）直链或支链化合物作为第二交联剂，所述直链或支链化合物在其中心含有氧化烯基并在其末端具有至少两个（甲基）丙烯酰基; （iii）电解质溶剂; （iv）电解质盐; 和（v）聚合引发剂。 此外，公开了通过聚合凝胶聚合物电解质组合物和包含凝胶聚合物电解质的电化学装置而形成的凝胶聚合物电解质。

    Thin film transistor array panel and manufacturing method thereof
    18.
    发明授权
    Thin film transistor array panel and manufacturing method thereof 失效
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US07501297B2

    公开(公告)日：2009-03-10

    申请号：US11336087

    申请日：2006-01-20

    申请人： Jang-Soo Kim ,  Soo-Jin Kim ,  Kyoung-Tai Han ,  Hee-Hwan Choe ,  Joo-Han Kim

    发明人： Jang-Soo Kim ,  Soo-Jin Kim ,  Kyoung-Tai Han ,  Hee-Hwan Choe ,  Joo-Han Kim

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1288 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/14692

    摘要： A method of manufacturing a thin film transistor array panel is provided, The method includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode on the semiconductor layer; depositing a passivation layer on the data line and the drain electrode; forming a photoresist including a first portion and a second portion thinner than the first portion on the passivation layer; etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode at least in part; removing the second portion of the photoresist; depositing a conductive film; and removing the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

    摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法。该方法包括：在基板上形成栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在半导体层上形成数据线和漏电极; 在数据线和漏电极上沉积钝化层; 在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂; 使用所述光致抗蚀剂作为掩模蚀刻所述钝化层，以至少部分地暴露所述漏电极的一部分; 去除光致抗蚀剂的第二部分; 沉积导电膜; 并且去除光致抗蚀剂以在漏电极的暴露部分上形成像素电极。

    Array substrate and method of manufacturing the same
    19.
    发明申请
    Array substrate and method of manufacturing the same 审中-公开
    阵列基板及其制造方法

    公开(公告)号：US20060238689A1

    公开(公告)日：2006-10-26

    申请号：US11407272

    申请日：2006-04-19

    申请人： Soo-Jin Kim ,  Dong-Ho Lee

    发明人： Soo-Jin Kim ,  Dong-Ho Lee

    IPC分类号： G02F1/1343

    CPC分类号： G02F1/136227 ,  G02F2001/13625 ,  G02F2001/136295

    摘要： An array substrate includes a first line, a second line and a switching element in a pixel region defined by the first and second lines adjacent to each other. The pixel electrode is electrically connected to an electrode of the switching element through a plurality of contact holes through which the electrode of the switching element is partially exposed.

    摘要翻译： 阵列基板包括由彼此相邻的第一和第二线限定的像素区域中的第一线，第二线和开关元件。 像素电极通过开关元件的电极部分露出的多个接触孔电连接到开关元件的电极。