公开(公告)号：US20030105949A1

公开(公告)日：2003-06-05

申请号：US09997987

申请日：2001-11-30

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC: H03K019/177 ,  H01L025/00 ,  G06F001/24 ,  G06F009/00

CPC classification number: G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit to provide an operating mode. The preferred executable information modules include configuration information interleaved with operand data, and may also include routing and power control information. The preferred ACE IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract translation: 本发明涉及用于自适应或可重新配置计算的新类别的集成电路的配置。 各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块以提供操作模式。 优选的可执行信息模块包括与操作数数据交错的配置信息，并且还可以包括路由和功率控制信息。 优选的ACE IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器 操作和位级操作。

公开(公告)号：US20020138716A1

公开(公告)日：2002-09-26

申请号：US09815122

申请日：2001-03-22

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Eugene Hogenauer ,  Walter James Scheuermann

IPC: G06F009/00

CPC classification number: G06F15/7867 ,  G06F13/4027 ,  Y02D10/12 ,  Y02D10/13

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Abstract translation: 本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。 优选的IC实施例包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器 操作和位级操作。 选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。

公开(公告)号：US20040243908A1

公开(公告)日：2004-12-02

申请号：US10683563

申请日：2003-10-10

Applicant: QuickSilver Technology, Inc.

Inventor： Brian Box ,  John M. Rudosky ,  Walter James Scheuermann

IPC: H03M013/00

CPC classification number: H03M13/3922 ,  H03M7/40 ,  H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H03M13/2792 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/4107 ,  H03M13/4161 ,  H03M13/6508 ,  H03M13/6511 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6519 ,  H03M13/6569

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements includes a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up-table memory and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner. The programmable shifter is programmable on a cycle-by-cycle basis and configured to perform an exclusive-or function on multiple shifted versions of its inputs. The programmable shifter is further programmable to implement a parallel linear feedback shift register which may be maskable. The programmable combiner is configured to perform packing on an input having variable input lengths to generate an output word having variable output lengths. The programmable combiner is further configured to perform bit interlacing and bit puncturing. Packing, bit interlacing and bit puncturing can be performed concurrently.

Abstract translation: 公开了可重新配置的位操作节点。 节点包括被配置为执行多个位向功能的执行单元和被配置为控制执行单元以允许执行面向位功能之一的控制单元。 执行单元包括彼此互连以允许执行面向位的功能的多个元件。 这些元件包括可编程蝶形单元，多个不可编程蝴蝶单元，多个数据路径元件，查找表存储器和重排序存储器。 执行单元能够参与多种操作模式之一来执行面向位的功能。 操作模式包括可编程模式和多种固定操作模式，包括维特比解码，turbo解码和可变长度编码和解码。 数据路径元件包括可编程移位器和可编程组合器。 可编程移位器可以逐个周期地编程，并且被配置为对其输入的多个移位版本执行排他或功能。 可编程移位器进一步可编程以实现可以被屏蔽的并行线性反馈移位寄存器。 可编程组合器被配置为在具有可变输入长度的输入上执行打包以生成具有可变输出长度的输出字。 可编程组合器还被配置为执行位隔行和位穿孔。 可以同时进行包装，位交织和位穿孔。

公开(公告)号：US20040034777A1

公开(公告)日：2004-02-19

申请号：US10223205

申请日：2002-08-16

Applicant: QuickSilver Technology, Inc.

Inventor： Eric Murray ,  Owen Robert Rubin

IPC: H04L009/00

CPC classification number: G06F21/16

Abstract: A system and apparatus for inserting a watermark into a compiled computer program selectively replaces specified optimizations by non-optimized code to encode bit values of the watermark. The watermark is read by decoding the executable code and assigning the decoded bit values, determined by the presence or absence of optimized code, to bit positions in a signature.

Abstract translation: 用于将水印插入到编译的计算机程序中的系统和装置通过非优化代码选择性地替换指定的优化以对水印的比特值进行编码。 通过解码可执行代码并将由优化的代码的存在或不存在确定的解码的位值分配给签名中的位位置来读取水印。

公开(公告)号：US20030115553A1

公开(公告)日：2003-06-19

申请号：US10022776

申请日：2001-12-13

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  W. James Scheuermann

IPC: G06F017/50

CPC classification number: G06F9/30189 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/325

Abstract: A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

Abstract translation: 一种微处理器架构，包括与用于执行微指令的微代码指令高速缓存组合的有限状态机。 通常会导致高重复循环操作的小序列的微指令在有限状态机（FSM）中实现。 使用FSM比缓存或寄存器集中的循环指令更节能。 此外，在执行微代码指令时，缓存或其他面向内存的方法的灵活性仍然可用。 通过ID标签将微指令识别为FSM操作（与高速缓存操作相反）。 微指令的其他领域可用于识别要使用的FSM电路的类型，直接配置FSM以实现微指令，指示某些字段将在一个或多个FSM和/或面向内存的操作中实现，例如 如缓存或注册。

公开(公告)号：US20030108012A1

公开(公告)日：2003-06-12

申请号：US10295632

申请日：2002-11-14

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04B007/216

CPC classification number: H04B1/708 ,  H04B1/70735 ,  H04B1/7083

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals.

Abstract translation: 提供了一种用于检测和识别发送扰码的基站或小区的身份的系统。 根据该系统的一个方面，该系统用于对组（8个）主小区进行扰码检测（每个扰码的X分量间隔十六（16）个码片）。 根据系统的另一方面，使用单个扰码发生器来产生主扰码。 然后，主扰码用于产生与接收信号相关使用的各个扰码，并行检测组中八（8）个可能的主小区中的哪一个发送接收信号。

公开(公告)号：US20030054774A1

公开(公告)日：2003-03-20

申请号：US10015544

申请日：2001-12-12

Applicant: Quicksilver Technology, Inc.

Inventor： Robert T. Plunkett ,  Ghobad Heidari ,  Paul L. Master

IPC: H04B001/40

CPC classification number: H04L29/06 ,  G06F15/7867 ,  H04L69/329 ,  H04W52/0209 ,  H04W88/02 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D70/142 ,  Y02D70/144

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions including a system acquisition function.

Abstract translation: 本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。 示例性IC实施例包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器 操作和位级操作。 选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。 在示例性实施例中，部分或全部计算元件被交替地配置为实现包括系统获取功能的两个或多个功能。

公开(公告)号：US20020181559A1

公开(公告)日：2002-12-05

申请号：US09871049

申请日：2001-05-31

Applicant: QuickSilver Technology, Inc.

Inventor： Ghobad Heidari-Bateni ,  Robert Thomas Plunkett

IPC: H04K001/00

CPC classification number: H04B1/711 ,  H04B1/7113 ,  H04B1/7117 ,  H04B1/712 ,  H04B2201/70709

Abstract: The present invention concerns a new type of rake receiver, namely, a multimode rake receiver, which may be included within either a mobile station or a base station, and which has dynamic pilot signal searching and multipath reception and combining capability, for CDMA, cdma2000, W-CDMA, or other mobile communication systems. The adaptive, multimode rake receiver includes a network interface, a plurality of adaptive multimode rake fingers, and a multimode processor. Each adaptive multimode rake finger and the multimode processor are responsive to first configuration information (a first mode signal) to configure for a path reception functional mode and are further responsive to second configuration information (a second mode signal) to configure for a searcher functional mode, providing the multimode rake receiver with acquisition, traffic, and idle modes. In the preferred embodiment, the multimode rake receiver is implemented using a new category of integrated circuitry for adaptive or reconfigurable computing, providing a plurality of heterogeneous computational elements coupled to an interconnection network, to form adaptive and reconfigurable multimode rake fingers and a multimode processor, for a plurality of different functional modes, including pilot signal searching and multipath reception and combination.

Abstract translation: 本发明涉及一种新型的耙式接收机，即可以包括在移动台或基站内的多模耙式接收机，并且具有动态导频信号搜索和多径接收和组合能力，适用于CDMA，cdma2000 ，W-CDMA或其他移动通信系统。 自适应多模Rake接收机包括网络接口，多个自适应多模耙指和多模式处理器。 每个自适应多模式耙指和多模式处理器响应于第一配置信息（第一模式信号）来配置路径接收功能模式，并且还响应于第二配置信息（第二模式信号）来配置搜索器功能模式 为多模Rake接收机提供采集，流量和空闲模式。 在优选实施例中，使用用于自适应或可重新配置计算的新类别的集成电路来实现多模耙式接收机，提供耦合到互连网络的多个异构计算元件，以形成自适应和可重新配置的多模式耙指和多模式处理器， 用于多种不同的功能模式，包括导频信号搜索和多径接收和组合。

公开(公告)号：US20040139428A1

公开(公告)日：2004-07-15

申请号：US10342888

申请日：2003-01-14

Applicant: QuickSilver Technology, Inc.

Inventor： Dan Chuang ,  Che Fang ,  Bicheng William Wu

IPC: G06F009/45

CPC classification number: G06F17/5045 ,  G06F9/4494

Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture. A dataflow language is used to define interconnections among hardware elements in the matrix datapath and controlled by FSM at run time and, thus, to determine hardware functionality at run time. The interconnectivity between the matrix datapath components, elements or resources, is capable of changing every clock cycle to optimize preferred calculations. The dataflow language is used to describe the optimized functions to an application programmer. The dataflow language is also compiled to a hardware definition that is used to create aspects of the desired functionality in silicon.

Abstract translation: 将以相对高级描述编写的数据流语言编译为硬件定义的系统。 然后，硬件定义用于在执行时或运行时在目标处理系统中配置数据流。 在优选实施例中，目标处理系统包括与有限状态机（FSM），共享存储器，板上存储器和其他资源通信的简化指令集计算机（RISC）处理器。 FSM主要用于加速矩阵运算，被认为是根据数据流定义进行配置的目标机器。 RISC处理器用作作为用于执行应用代码的主机处理器的外部中央处理器（CPU）的协处理器。 其他实施例可以在任何其他处理架构中使用本发明的方面。 数据流语言用于定义矩阵数据路径中的硬件元素之间的互连，并在运行时由FSM控制，从而在运行时确定硬件功能。 矩阵数据路径组件，元素或资源之间的互连能力可以改变每个时钟周期以优化优选的计算。 数据流语言用于描述应用程序员的优化功能。 数据流语言也被编译为硬件定义，用于创建硅中所需功能的方面。

公开(公告)号：US20040133745A1

公开(公告)日：2004-07-08

申请号：US10626833

申请日：2003-07-23

Applicant: QuickSilver Technology, Inc.

Inventor： Amit Ramchandran

IPC: G06F012/00

CPC classification number: G06F13/287 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3867 ,  G06F9/3885 ,  G06F13/16

Abstract: The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.

Abstract translation: 本发明包括具有几个特征的适应性高性能节点（RXN），使其能够提供高性能以及适应性。 RXN的优选实施例包括运行时可配置数据路径和控制路径。 RXN支持包括8,16,24和32位代码的多精度算术。 可以重新配置数据流，以最小化不同操作的寄存器访问。 例如，通过重新配置数据路径，可以通过最小或不存在寄存器存储来执行乘法累加操作。 可以在建立阶段期间配置预定的内核，使得RXN可以有效地执行例如离散余弦变换（DCT），快速傅里叶变换（FFT）和其他操作。 提供其他功能。