Abstract:
Methods and apparatus to protect a protocol interface are described herein. In an example method, a driver request is received during an operation phase of firmware in a processor system. The driver request may be identified as a request associated with a violating condition of the protocol interface. Accordingly, the driver request is rejected.
Abstract:
The present invention provides a system for creating an application software environment without changing an operating system of a client computer, the system comprising an operating system abstraction and protection layer, wherein said abstraction and protection layer is interposed between a running software application and said operating system, whereby a virtual environment in which an application may run is provided and application level interactions are substantially removed. Preferably, any changes directly to the operating system are selectively made within the context of the running application and the abstraction and protection layer dynamically changes the virtual environment according to administrative settings. Additionally, in certain embodiments, the system continually monitors the use of shared system resources and acts as a service to apply and remove changes to system components. The present thus invention defines an nullOperating System Guard.null These components cover the protection semantics required by DLLs and other shared library code as well as system device drivers, fonts, registries and other configuration items, files, and environment variables.
Abstract:
A procedure identifies a program image and generates a basic block flow graph associated with the program image. Execution of the program image is benchmarked and the basic block flow graph is annotated with the results of the benchmarking of the program image. Basic blocks of the program are then grouped into bins. When the program image is executed, a drafting scheduler stops threads before they leave a bin and schedules any threads queued for the same bin.
Abstract:
The present invention is generally directed to an apparatus and method for performing a partial flush of a processor pipeline in response to exceptions (e.g., interrupts). In accordance with an aspect of one embodiment a processor is provided with logic that operates to flush only limited stages of a processor pipepline (e.g., stages between the current instruction and the pending interrupt) if the execution of a current instruction will impact the execution of a pending interrupt (e.g., if the current instruction is a branch, if the current instruction would cause the processor to enter a mode that disables the pending interrupt, etc.). In accordance with another aspect of this embodiment, a method is provided for performing a partial flush of processor pipeline if the execution of a current instruction would impact the execution of a pending interrupt.
Abstract:
According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.
Abstract:
A method to efficiently implement a null reference check has been disclosed. The method comprises executing a speculative load instruction to load data from an address, checking whether the speculative load instruction execution fails, and raising a null reference exception if the speculative load instruction fails. In one embodiment, the method includes executing a speculative load instruction to load data from an address that includes a base address, checking whether the speculative load instruction execution fails, and checking whether the base address is null if the speculative load instruction execution fails.
Abstract:
A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
Abstract:
A software enabled, matrix switch is presented wherein a scalable plurality of inputs, coupled to media content sources, provide media content which is recursively routed through select media processing object(s) coupled to a scalable plurality of matrix switch outputs in accordance with a user-defined media processing project.
Abstract:
A system which will allow a bill acceptor and dispenser to be incorporated into a vending machine operating on a standardized vending machine protocol to allow the vending machine to dispense change in the form of coins and/or currency according to the amount of change to be dispensed and the availability of specific denominations of coins and currency.
Abstract:
A voltage reference is dynamically and digitally controlled by a digital function. The digital function may be implemented as a digital calculation or look up table. Inputs to the function include a modifiable trim value stored in a trim register, and a substrate temperature value. The preset value of the trim register is a trim preset value generated by cutting fuses and/or leaving fuses uncut. The cutting may be performed using laser trimming-devices. The output of the digital function is a corrected reference trim value that controls the gain of a voltage reference amplifier whose input is a band gap based voltage reference, and whose output is a derived voltage reference. The substrate temperature value is provided by a monolithic temperature monitor whose sensor may be on the same die as the derived voltage reference. The derived voltage reference provides a stable reference voltage that is dynamically and digitally controllable, to a host system that requires a voltage reference.