公开(公告)号：US20040255101A1

公开(公告)日：2004-12-16

申请号：US10458457

申请日：2003-06-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael A. Filippo ,  James K. Pickett ,  Benjamin T. Sander ,  Rama S. Gopal

IPC: G06F009/00

CPC classification number: G06F9/3842 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/3861

Abstract: A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.

Abstract translation: 微处理器可以包括被配置为发布操作的调度器和被配置为执行由调度器发出的存储器操作的加载存储单元。 加载存储单元被配置为存储识别发送到加载存储单元的存储器操作的信息。 响应于检测到所发出的存储器操作之一的不正确的数据推测，加载存储单元被配置为通过向调度器提供指示来重播所发布的存储器操作中的至少一个。 调度器被配置为响应地重新发出由加载存储单元识别的存储器操作。