公开(公告)号：US20040093465A1

公开(公告)日：2004-05-13

申请号：US10628036

申请日：2003-07-24

Applicant: QuickSilver Technology, Inc.

Inventor： Amit Ramchandran

IPC: G06F012/00

CPC classification number: G06F13/287 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3867 ,  G06F9/3885 ,  G06F13/16

Abstract: A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number of data address generators are connected with a memory unit and the data buses. The data address generators retrieve data values from the memory unit and communicate the data values to the data buses without latency. The data address generators are adapted to simultaneously communicate each of the data values to a different data bus without latency. The cache memory units are adapted to simultaneously load data values from the data buses, with each data value loaded into a different cache line without latency.

Abstract translation: 分布式数据高速缓存包括多个高速缓冲存储器单元或每个具有多个高速缓存行的寄存器文件。 数据总线与高速缓冲存储器单元连接。 每个数据总线与来自每个高速缓冲存储器单元的不同的高速缓存线连接。 多个数据地址发生器与存储器单元和数据总线连接。 数据地址发生器从存储器单元检索数据值，并将数据值传送到数据总线，而不会有延迟。 数据地址发生器适于同时将每个数据值传送到不同的数据总线，而无需等待时间。 高速缓冲存储器单元适于同时从数据总线加载数据值，其中每个数据值被加载到不同的高速缓存行中而没有延迟。

公开(公告)号：US20030204575A1

公开(公告)日：2003-10-30

申请号：US10135905

申请日：2002-04-29

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  John Watson

IPC: G06F015/177

CPC classification number: G06Q30/06 ,  H04W8/245 ,  Y10S707/99932

Abstract: A system for permitting new, or enhanced, functionality to be transferred to an adaptable device. In a preferred embodiment, the permitted functionality is determined according to an accounting method associated with a user's account. This approach allows a user to contract for specific services, functionality, etc. regardless of changes over time such as changes to data formats, communication protocols, external devices or infrastructure, etc. In a preferred embodiment, the functionality is stored on a ubiquitous communications network such as the Internet. Functionality is transferred to different devices as digital information over the network. This allows hardware functionality to be licensed in many forms. For example, site licenses can be obtained for companies; hardware nulltrialwarenull can be provided to allow limited functionality for a limited time for lower-cost payments, etc.

公开(公告)号：US20030108203A1

公开(公告)日：2003-06-12

申请号：US10015531

申请日：2001-12-12

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04K001/00

CPC classification number: H04B1/70752 ,  H04B1/70735 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7095

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding segment of the master scrambling code. For every sixteen (16) chips, a new segment of the master scrambling code is introduced into one of the correlators, a segment of the master scrambling code is dropped from another correlator, and segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding segments of the master scrambling code and newly received signals.

Abstract translation: 提供了一种用于检测和识别发送扰码的基站或小区的身份的系统。 根据系统的一个方面，该系统用于执行八（8）个主小区（每个扰码分开间隔十六（16）个码片）的扰码检测）。 根据系统的另一方面，使用单个扰码发生器来产生主扰码。 然后，主扰码用于产生与接收信号相关使用的各个扰码，并行检测组中八（8）个可能的主小区中的哪一个发送接收信号。 根据系统的另一方面，每个相关器维护主扰码的相应段。 对于每十六（16）个芯片，主扰码的一个新的段被引入到一个相关器中，主扰码的一个段从另一个相关器中丢弃，主扰码的段被顺序地移位或传播通过 剩余的相关器; 并且相关器使用它们各自对应的主扰码和新接收的信号段执行并发相关。

公开(公告)号：US20040143724A1

公开(公告)日：2004-07-22

申请号：US10673678

申请日：2003-09-29

Applicant: QuickSilver Technology, Inc.

Inventor： Rojit Jacob ,  Dan MingLun Chuang

IPC: G06F015/00

CPC classification number: G06F15/7867 ,  G06F15/17381

Abstract: The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing.

Abstract translation: 本发明提供一种自适应计算引擎（ACE），其包括具有不同能力的处理节点，例如算术节点，位操作节点，有限状态机节点，输入/输出节点和可编程标量节点（PSN）。 根据本发明的一个实施例，公共架构适用于在内核节点或k节点中或作为通用RISC节点的功能。 k节点充当系统控制器，负责调整其他节点执行选定的功能。 作为RISC节点，PSN被配置为执行诸如信号处理的计算密集型应用。

公开(公告)号：US20040093479A1

公开(公告)日：2004-05-13

申请号：US10628083

申请日：2003-07-24

Applicant: QuickSilver Technology, Inc.

Inventor： Amit Ramchandran

IPC: G06F009/30

CPC classification number: G06F13/287 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3867 ,  G06F9/3885 ,  G06F13/16

Abstract: A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the identified instructions with an index value in the set of instructions before the identified instructions and replacing at least one instance of the frequently executed instructions subsequent to the explicit caching instruction with a compressed instruction referencing the index value. One or more instructions can be identified for compression, including groups of consecutive or non-consecutive instructions. The explicit caching instruction directs a node in an adaptive computing machine to store instructions in an instruction storage unit in association with an index value. Instructions stored in the storage unit are retrievable with reference to the index value. The compressed instruction may include one or more references to index values, and can include a sequence of index values indicating the sequence of execution of the associated instructions.

Abstract translation: 一种用于在自适应计算机器中压缩一组指令的方法包括识别频繁执行的指令，将识别出的指令与所识别的指令之前的指令集中的索引值相关联的显式高速缓存指令，并将所述指令的至少一个实例 在显式高速缓存指令之后的执行指令具有引用索引值的压缩指令。 可以识别一个或多个指令用于压缩，包括连续或非连续指令的组。 显式高速缓存指令引导自适应计算机中的节点将指令存储在与索引值相关联的指令存储单元中。 存储在存储单元中的指令可以参考索引值进行检索。 压缩指令可以包括对索引值的一个或多个引用，并且可以包括指示相关联指令的执行顺序的索引值序列。

公开(公告)号：US20040068716A1

公开(公告)日：2004-04-08

申请号：US10264485

申请日：2002-10-04

Applicant: Quicksilver Technology, Inc.

Inventor： Cameron Stevens

IPC: G06F009/45

CPC classification number: G06F8/47

Abstract: The invention provides a compiler for generating assembly or configuration instructions from source code for an integrated circuit architecture of a plurality of different IC architectures. The source code is represented as a plurality of nodes of an abstract syntax tree. For each target architecture, a plurality of concrete instruction tiles are generated as concrete classes corresponding to and inheriting from a plurality of function tiles. Each function tile is implemented as an abstract class, represents a corresponding function, such as an ADD or MULT function, and implements a matching operation for the corresponding function. The compiler includes an instruction selector, formed as an abstract class, which implements a matching function and instruction generation for the abstract syntax tree by calling the corresponding matching operations of the concrete instruction tiles, inherited from the plurality of function tiles. When a concrete instruction tile or corresponding function has been matched to a node of the abstract syntax tree, the instruction selector calls an instruction generation function of the corresponding concrete instruction tile to generate an instruction for the corresponding IC architecture. By varying the concrete instruction tiles, the compiler may be targeted to any IC architecture.

Abstract translation: 本发明提供了一种用于从用于多个不同IC架构的集成电路架构的源代码生成汇编或配置指令的编译器。 源代码被表示为抽象语法树的多个节点。 对于每个目标架构，生成多个具体指令块作为与多个功能块相对应并从其继承的具体类。 每个功能块实现为抽象类，表示相应的功能，如ADD或MULT功能，并为相应的功能实现匹配操作。 编译器包括形成为抽象类的指令选择器，其通过调用从多个功能块继承的具体指令块的相应匹配操作来实现抽象语法树的匹配函数和指令生成。 当具体的指令块或对应的功能与抽象语法树的节点匹配时，指令选择器调用相应具体指令块的指令生成函数，以生成相应IC架构的指令。 通过改变具体的指令块，编译器可以针对任何IC架构。

公开(公告)号：US20040015971A1

公开(公告)日：2004-01-22

申请号：US10189791

申请日：2002-07-03

Applicant: Quicksilver Technology, Inc.

Inventor： Paul L. Spoltore ,  Ramana V. Katragadda

IPC: G06F009/00

CPC classification number: G06F9/4887

Abstract: A method of selecting tasks for execution on a processing node is provided. A plurality of indications of execution times corresponding to a first plurality of tasks is received. Also, a plurality of indications of maximum allowable latencies corresponding to the first plurality of tasks is received. At least a subset of the first plurality of tasks is selected for execution on the processing node based on the plurality of indications of execution times and the plurality of indications of maximum allowable latencies.

Abstract translation: 提供了一种在处理节点上选择执行任务的方法。 接收对应于第一多个任务的多个执行时间指示。 此外，接收对应于第一多个任务的多个最大允许延迟的指示。 基于执行时间的多个指示和最大允许延迟的多个指示，选择第一多个任务的至少一个子集用于在处理节点上执行。

公开(公告)号：US20040008640A1

公开(公告)日：2004-01-15

申请号：US10067496

申请日：2002-02-04

Applicant: QuickSilver Technology, Inc.

Inventor： Ghobad Heidari ,  Kuor-Hsin Chang

IPC: H04B007/216

CPC classification number: G06F15/7867 ,  H04B1/708 ,  H04B2201/70711

Abstract: A system for implementing a searcher for use with a communication device is provided. According to one aspect of the system, the searcher includes one or more computational units which are used to perform a PN sequence generation function to generate a sequence of PN codes. The searcher further includes a number of computational units which are used to correlate received signal samples with the PN codes. As each signal sample is received by the communication device, the received signal sample is correlated with a first PN sequence in a parallel manner using the computational units. The correlation results are then accumulated. As the next signal sample is received, this newly received signal sample is similarly correlated with the next PN sequence in a parallel manner. Likewise, the correlation results are accumulated with the previous correlation results. The foregoing process is repeated until all the signal samples needed for correlation are received and correlated with sequences of PN codes. According to another aspect of the system, the a computational units are implemented using adaptive hardware resources. The number of computational units which are used to implement the correlation function is adjustable depending on, for example, the amount of available adaptive hardware resources.

Abstract translation: 提供了一种用于实现与通信设备一起使用的搜索器的系统。 根据该系统的一个方面，搜索器包括一个或多个计算单元，用于执行PN序列生成功能以产生PN码序列。 搜索器还包括多个计算单元，用于将接收到的信号采样与PN码相关联。 由于每个信号采样由通信设备接收，所以接收的信号样本使用计算单元并行地与第一PN序列相关。 然后累积相关结果。 当接收到下一个信号样本时，新接收的信号样本与下一个PN序列以并行方式类似地相关。 同样地，相关结果与先前的相关结果一起累积。 重复上述过程，直到接收到相关所需的所有信号样本并与PN码的序列相关联。 根据系统的另一方面，使用自适应硬件资源来实现计算单元。 用于实现相关函数的计算单元的数量可以根据例如可用的自适应硬件资源的量来调整。

公开(公告)号：US20030227884A1

公开(公告)日：2003-12-11

申请号：US10015537

申请日：2001-12-12

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04B007/216

CPC classification number: H04B1/708 ,  H04B1/70735 ,  H04B1/7083

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals.

Abstract translation: 提供了一种用于检测和识别发送扰码的基站或小区的身份的系统。 根据系统的一个方面，该系统用于执行八（8）个主小区（每个扰码分开间隔十六（16）个码片）的扰码检测）。 根据系统的另一方面，使用单个扰码发生器来产生主扰码。 然后，主扰码用于产生与接收信号相关使用的各个扰码，并行检测组中八（8）个可能的主小区中的哪一个发送接收信号。

公开(公告)号：US20030140123A1

公开(公告)日：2003-07-24

申请号：US10040100

申请日：2002-01-04

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Bohumir Uvacek

IPC: G06F015/177

CPC classification number: H04W88/06 ,  H04W48/12

Abstract: The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions.

Abstract translation: 本发明提供了一种用于配置自适应集成电路的方法和装置，以在诸如蜂窝电话，GSM电话，另一类型的移动电话或移动台之类的通信设备中提供一个或多个操作模式或其它功能，或 任何其他类型的媒体通信设备，包括视频，语音或无线电，或其他形式的多媒体。 自适应集成电路被配置和重新配置用于多个任务，例如信道获取，语音传输或多媒体和其他数据处理。 在优选实施例中，发生配置和重新配置以随时间自适应地优化特定活动的性能，例如增加频道获取的速度，增加吞吐率，增加感知语音和媒体质量，以及降低丢弃通信的速率 会话