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    Device Fabrication by Anisotropic Wet Etch
    11.
    发明申请
    Device Fabrication by Anisotropic Wet Etch 失效
    各向异性湿蚀刻器件制造

    公开(公告)号：US20080246059A1

    公开(公告)日：2008-10-09

    申请号：US12141878

    申请日：2008-06-18

    Applicant: Yujun Li ,  Kenneth T. Settlemyer ,  Jochen Beintner

    Inventor： Yujun Li ,  Kenneth T. Settlemyer ,  Jochen Beintner

    IPC: H01L29/772 ,  H01L21/306

    CPC classification number: H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

    Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

    Abstract translation: 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 制造基于Si的材料基座，其顶表面和其侧壁的取向方向基本上平行于基座和支撑构件的选定结晶平面。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

    METHOD AND APPARATUS FOR PARALLEL DATA PREPARATION AND PROCESSING OF INTEGRATED CIRCUIT GRAPHICAL DESIGN DATA
    12.
    发明申请
    METHOD AND APPARATUS FOR PARALLEL DATA PREPARATION AND PROCESSING OF INTEGRATED CIRCUIT GRAPHICAL DESIGN DATA 失效
    用于并行数据准备和处理集成电路图形设计数据的方法和装置

    公开(公告)号：US20080077891A1

    公开(公告)日：2008-03-27

    申请号：US11535789

    申请日：2006-09-27

    Applicant: Daria R. Dooling ,  Kenneth T. Settlemyer ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

    Inventor： Daria R. Dooling ,  Kenneth T. Settlemyer ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

    Abstract translation: 一种用于实现ORC过程以促进集成电路（IC）图形设计的物理验证的方法。 该方法包括：通过主机将IC图形设计数据划分成文件，使得文件对应于具有定义边距的感兴趣区域或分区，将分割的数据文件分散到网络内的可用CPU，通过cpu接收处理每个作业 文件，其中检测和去除在划分期间由分割边缘的二分分割产生的伪像，包括切割引起的错误错误，并且将这些伪像误差的形状改变效果最小化，并将每个cpu处理的结果传送到 主机用于聚合处理。

    Pull-back method of forming fins in FinFets
    13.
    发明授权
    Pull-back method of forming fins in FinFets 失效
    在FinFets中形成翅片的回拉法

    公开(公告)号：US07018551B2

    公开(公告)日：2006-03-28

    申请号：US10730234

    申请日：2003-12-09

    Applicant: Jochen C. Beintner ,  Dureseti Chidambarrao ,  Yujun Li ,  Kenneth T. Settlemyer, Jr.

    Inventor： Jochen C. Beintner ,  Dureseti Chidambarrao ,  Yujun Li ,  Kenneth T. Settlemyer, Jr.

    IPC: B44C1/22

    CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

    Abstract: A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.

    Abstract translation: 一种形成具有FinFET晶体管的集成电路的方法包括形成次光刻鳍片的方法，其中限定包含一对鳍片的硅块的掩模，所述掩模的宽度被减小或者被拉回每边的一个鳍片的厚度， 之后在第一掩模周围形成第二掩模，使得在去除第一掩模之后，在第二掩模中保留具有一对散热片之间的间隔距离的宽度的孔。 当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过拉回步骤限定翅片厚度。 一种替代方法是使用相反极性的光刻法，首先在两个散热片之间光刻地限定中心蚀刻孔径，然后通过拉回步骤扩大孔径的宽度，以便用耐蚀刻塞子填充加宽的孔径限定了 一对翅片，从而设置翅片宽度而没有对准kstep。

    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
    14.
    发明授权
    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
    用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构

    公开(公告)号：US06936512B2

    公开(公告)日：2005-08-30

    申请号：US10260085

    申请日：2002-09-27

    Applicant: Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    Inventor： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    IPC: H01L21/314 ,  H01L21/316 ,  H01L21/8242

    CPC classification number: H01L29/66181 ,  H01L21/3144 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10864 ,  H01L27/10867

    Abstract: Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

    Abstract translation: 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。

    Vertical semiconductor devices
    15.
    发明授权
    Vertical semiconductor devices 失效
    垂直半导体器件

    公开(公告)号：US06887761B1

    公开(公告)日：2005-05-03

    申请号：US10708647

    申请日：2004-03-17

    Applicant: Hiroyuki Akatsu ,  Thomas W. Dyer ,  Ravikumar Ramachandran ,  Kenneth T. Settlemyer, Jr.

    Inventor： Hiroyuki Akatsu ,  Thomas W. Dyer ,  Ravikumar Ramachandran ,  Kenneth T. Settlemyer, Jr.

    IPC: H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01I29/76

    CPC classification number: H01L29/66666 ,  H01L21/2257 ,  H01L21/76224 ,  H01L29/7827

    Abstract: A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.

    Abstract translation: 一种用于增加垂直半导体器件的阈值电压的方法和结构。 该方法包括在其半导体材料具有垂直于衬底表面的取向平面的衬底中形成深沟槽。 然后，在深沟槽的深度周围形成垂直晶体管。 接下来，形成两个浅沟槽隔离，使得它们在有源区域中夹住深沟槽，并且两个浅沟槽隔离区域经由垂直于取向平面的平面邻接有源区。 然后，垂直晶体管的沟道区域暴露在深沟槽中的大气中，然后化学蚀刻到平行于取向平面的平面上。 然后，在深沟槽的壁上形成栅极电介质层。 最后，深沟槽充满多晶硅，形成垂直晶体管的栅极。

    Corner clipping for field effect devices
    18.
    发明授权
    Corner clipping for field effect devices 有权
    场效应装置的角剪

    公开(公告)号：US07666741B2

    公开(公告)日：2010-02-23

    申请号：US11333109

    申请日：2006-01-17

    Applicant: Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    Inventor： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    IPC: H01L21/336

    CPC classification number: H01L21/30608 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7853

    Abstract: A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.

    Abstract translation: 提出了一种用于制造非平面场效应器件的方法。 该方法包括生产Si基材料Fin结构，其具有与Si Fin结构的{111}晶面基本上平行的顶表面，并且用含有氢氧化铵（NH 4 OH）的溶液蚀刻Si Fin结构 ）。 以这种方式，由于各种Si基材料结晶面的氢氧化铵中的蚀刻速率不同，Fin结构上的拐角被限制，Fin结构的水平和垂直平面之间的角度增加。 然后制造具有夹角或圆角的FinFET器件以完成。 在典型的实施例中，FinFET器件被选择为绝缘体上硅（SOI）器件。

    Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data
    20.
    发明授权
    Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data 失效
    用于并行数据准备和处理集成电路图形设计数据的方法和装置

    公开(公告)号：US07434185B2

    公开(公告)日：2008-10-07

    申请号：US11535789

    申请日：2006-09-27

    Applicant: Daria R. Dooling ,  Kenneth T. Settlemyer, Jr. ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

    Inventor： Daria R. Dooling ,  Kenneth T. Settlemyer, Jr. ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

    Abstract translation: 一种用于实现ORC过程以促进集成电路（IC）图形设计的物理验证的方法。 该方法包括：通过主机将IC图形设计数据划分成文件，使得文件对应于具有定义边距的感兴趣区域或分区，将分割的数据文件分散到网络内的可用CPU，通过cpu接收处理每个作业 文件，其中检测和去除在划分期间由分割边缘的二分分割产生的伪像，包括切割引起的错误错误，并且将这些伪像误差的形状改变效果最小化，并将每个cpu处理的结果传送到 主机用于聚合处理。

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